Simulation Results: dma

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 81.17 %
  • code
  • 91.85 %
  • assert
  • 95.55 %
  • func
  • 56.11 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 538.284us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 323.816us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1919.037us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 15.258us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 43.434us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 1978.058us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 145.405us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 69.479us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 43.434us 1 1 100.00
dma_csr_aliasing 4.000s 145.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 54.000s 16240.110us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 727.000s 229671.771us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 102.000s 38752.386us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 102.000s 38752.386us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 727.000s 229671.771us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 174.000s 144514.342us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 102.000s 38752.386us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 1624.413us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 39.000s 3252.258us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 36.569us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 14.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 4.000s 106.646us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 4.000s 106.646us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 15.258us 1 1 100.00
dma_csr_rw 2.000s 43.434us 1 1 100.00
dma_csr_aliasing 4.000s 145.405us 1 1 100.00
dma_same_csr_outstanding 2.000s 187.749us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 15.258us 1 1 100.00
dma_csr_rw 2.000s 43.434us 1 1 100.00
dma_csr_aliasing 4.000s 145.405us 1 1 100.00
dma_same_csr_outstanding 2.000s 187.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 9.000s 103.264us 1 1 100.00
dma_generic_stress 174.000s 144514.342us 1 1 100.00
dma_handshake_stress 102.000s 38752.386us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1482.463us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 780.244us 1 1 100.00
dma_sec_cm 2.000s 10.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 41.000s 4201.244us 1 1 100.00
dma_longer_transfer 4.000s 314.579us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 989.096us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 8062396321966229610370104405049559517047702500130673882976744312728440626610 95
UVM_INFO @ 989095622ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---