Simulation Results: edn/edn1

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.39 %
  • code
  • 83.26 %
  • assert
  • 97.14 %
  • func
  • 78.78 %
  • line
  • 98.10 %
  • branch
  • 93.72 %
  • cond
  • 90.00 %
  • toggle
  • 87.87 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 30.377us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 16.010us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 27.851us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.180s 1386.713us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.100s 24.709us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.100s 20.527us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 27.851us 1 1 100.00
edn_csr_aliasing 1.100s 24.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.220s 41.627us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.220s 41.627us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.220s 41.627us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.980s 39.988us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.190s 174.283us 1 1 100.00
errs 1 1 100.00
edn_err 1.080s 49.098us 1 1 100.00
disable 2 2 100.00
edn_disable 0.970s 22.291us 1 1 100.00
edn_disable_auto_req_mode 1.090s 60.506us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.770s 77.667us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 43.115us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 29.865us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.540s 132.177us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.540s 132.177us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 16.010us 1 1 100.00
edn_csr_rw 0.850s 27.851us 1 1 100.00
edn_csr_aliasing 1.100s 24.709us 1 1 100.00
edn_same_csr_outstanding 1.150s 17.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 16.010us 1 1 100.00
edn_csr_rw 0.850s 27.851us 1 1 100.00
edn_csr_aliasing 1.100s 24.709us 1 1 100.00
edn_same_csr_outstanding 1.150s 17.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
edn_tl_intg_err 1.870s 644.350us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.090s 16.483us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.190s 174.283us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.190s 174.283us 1 1 100.00
edn_sec_cm 3.010s 156.472us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.190s 174.283us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.870s 644.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 44.980s 4569.103us 1 1 100.00