Simulation Results: hmac

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.78 %
  • code
  • 98.02 %
  • assert
  • 96.70 %
  • func
  • 44.61 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.980s 4925.332us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 39.042us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.770s 15.915us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.200s 2389.953us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.360s 360.446us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 140.620s 20225.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.770s 15.915us 1 1 100.00
hmac_csr_aliasing 5.360s 360.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.410s 1161.402us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 4.840s 407.924us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.820s 665.481us 1 1 100.00
hmac_test_sha384_vectors 438.180s 12381.861us 1 1 100.00
hmac_test_sha512_vectors 20.870s 243.838us 1 1 100.00
hmac_test_hmac256_vectors 7.520s 510.514us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 607.068us 1 1 100.00
hmac_test_hmac512_vectors 10.440s 395.002us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.320s 5250.213us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 56.780s 2185.245us 1 1 100.00
error 1 1 100.00
hmac_error 53.510s 15693.866us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 82.190s 25222.348us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.980s 4925.332us 1 1 100.00
hmac_long_msg 26.410s 1161.402us 1 1 100.00
hmac_back_pressure 4.840s 407.924us 1 1 100.00
hmac_datapath_stress 56.780s 2185.245us 1 1 100.00
hmac_burst_wr 13.320s 5250.213us 1 1 100.00
hmac_stress_all 605.230s 28561.228us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.980s 4925.332us 1 1 100.00
hmac_long_msg 26.410s 1161.402us 1 1 100.00
hmac_back_pressure 4.840s 407.924us 1 1 100.00
hmac_datapath_stress 56.780s 2185.245us 1 1 100.00
hmac_wipe_secret 82.190s 25222.348us 1 1 100.00
hmac_test_sha256_vectors 9.820s 665.481us 1 1 100.00
hmac_test_sha384_vectors 438.180s 12381.861us 1 1 100.00
hmac_test_sha512_vectors 20.870s 243.838us 1 1 100.00
hmac_test_hmac256_vectors 7.520s 510.514us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 607.068us 1 1 100.00
hmac_test_hmac512_vectors 10.440s 395.002us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.980s 4925.332us 1 1 100.00
hmac_long_msg 26.410s 1161.402us 1 1 100.00
hmac_back_pressure 4.840s 407.924us 1 1 100.00
hmac_datapath_stress 56.780s 2185.245us 1 1 100.00
hmac_burst_wr 13.320s 5250.213us 1 1 100.00
hmac_error 53.510s 15693.866us 1 1 100.00
hmac_wipe_secret 82.190s 25222.348us 1 1 100.00
hmac_test_sha256_vectors 9.820s 665.481us 1 1 100.00
hmac_test_sha384_vectors 438.180s 12381.861us 1 1 100.00
hmac_test_sha512_vectors 20.870s 243.838us 1 1 100.00
hmac_test_hmac256_vectors 7.520s 510.514us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 607.068us 1 1 100.00
hmac_test_hmac512_vectors 10.440s 395.002us 1 1 100.00
hmac_stress_all 605.230s 28561.228us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 605.230s 28561.228us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.720s 15.168us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 13.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.340s 226.862us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.340s 226.862us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 39.042us 1 1 100.00
hmac_csr_rw 0.770s 15.915us 1 1 100.00
hmac_csr_aliasing 5.360s 360.446us 1 1 100.00
hmac_same_csr_outstanding 0.990s 95.822us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 39.042us 1 1 100.00
hmac_csr_rw 0.770s 15.915us 1 1 100.00
hmac_csr_aliasing 5.360s 360.446us 1 1 100.00
hmac_same_csr_outstanding 0.990s 95.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.950s 642.275us 1 1 100.00
hmac_tl_intg_err 1.830s 86.356us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.830s 86.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.980s 4925.332us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.920s 352.663us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 43.920s 3565.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.270s 150.994us 1 1 100.00