Simulation Results

Simulation Results: i2c

07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.82 %

code
81.99 %

assert
96.19 %

func
79.28 %

line
96.75 %

branch
92.69 %

cond
85.04 %

toggle
89.66 %

FSM
45.83 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	24.140s	1782.806us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	30.420s	2899.983us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.750s	46.734us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.780s	72.431us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.050s	1017.188us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.820s	205.775us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.760s	26.635us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.780s	72.431us	1	1	100.00
	i2c_csr_aliasing	1.820s	205.775us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	4.040s	315.040us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3.820s	213.912us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	41.700s	1324.095us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.700s	24.687us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	53.860s	3210.348us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	99.500s	5176.440us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.180s	802.142us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.910s	520.148us	1	1	100.00
	i2c_host_fifo_reset_rx	4.370s	739.628us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	83.370s	9115.100us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	27.090s	967.351us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.130s	318.356us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.160s	2198.696us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	185.420s	51534.486us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.720s	3429.376us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	5.690s	543.961us	1	1	100.00
	i2c_target_intr_smoke	4.030s	1616.597us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.490s	395.916us	1	1	100.00
	i2c_target_fifo_reset_tx	1.590s	200.900us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	2.700s	9049.655us	1	1	100.00
	i2c_target_stress_rd	5.690s	543.961us	1	1	100.00
	i2c_target_intr_stress_wr	13.770s	13583.947us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.840s	1345.529us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.060s	221.996us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.140s	846.283us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	8.930s	10160.151us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.820s	1580.706us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.910s	47.396us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	41.700s	1324.095us	1	1	100.00
	i2c_host_perf_precise	76.070s	3021.693us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	27.090s	967.351us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.530s	146.079us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.450s	1035.233us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.120s	572.383us	1	1	100.00
	i2c_target_nack_txstretch	1.310s	208.810us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.780s	2325.842us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.850s	527.313us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.900s	19.170us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.690s	14.694us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.370s	75.584us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.370s	75.584us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	46.734us	1	1	100.00
	i2c_csr_rw	0.780s	72.431us	1	1	100.00
	i2c_csr_aliasing	1.820s	205.775us	1	1	100.00
	i2c_same_csr_outstanding	1.210s	38.850us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	46.734us	1	1	100.00
	i2c_csr_rw	0.780s	72.431us	1	1	100.00
	i2c_csr_aliasing	1.820s	205.775us	1	1	100.00
	i2c_same_csr_outstanding	1.210s	38.850us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.150s	155.597us	1	1	100.00
	i2c_sec_cm	1.050s	274.527us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.150s	155.597us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.140s	3796.272us	1
target_error_intr				1
	i2c_target_unexp_stop	0.950s	68.422us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.000s	44.347us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	58430310390527760835358882701080656186163469849917537124811491749172611636092	112	UVM_INFO @ 315040458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	80369954697552200362830303310641623815218677262043402124763324800371758121872	134	UVM_INFO @ 213911627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	5257154788314980202973885622412471191741628376329520075100165344654996157703	98	UVM_INFO @ 44347200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	113825881419103256519122851193344860657815517954261589534521272820726519133947	84	UVM_INFO @ 2198695957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	50129453490036333647393262722609817436645925462672867383322770342357716291103	78	UVM_INFO @ 68422248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	79575133465043972130756188857165514513043190690572672587833361325523602844226	79	UVM_INFO @ 10160150982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	115276231644781602751339095858211664069276730689763951360626363771271612074126	89	UVM_INFO @ 3796272359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---