Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.69 %
  • code
  • 84.86 %
  • assert
  • 95.85 %
  • func
  • 91.37 %
  • line
  • 97.80 %
  • branch
  • 96.34 %
  • cond
  • 79.18 %
  • toggle
  • 89.15 %
  • FSM
  • 61.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.380s 190.821us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 14.935us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 13.654us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 214.951us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 16.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.010s 25.158us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 13.654us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 16.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.700s 58.323us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.050s 263.089us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 22.458us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.470s 100.039us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.190s 224.434us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_prog_failure 2.470s 100.039us 1 1 100.00
lc_ctrl_errors 4.190s 224.434us 1 1 100.00
lc_ctrl_security_escalation 7.780s 1484.456us 1 1 100.00
lc_ctrl_jtag_state_failure 21.910s 1828.690us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.990s 1263.505us 1 1 100.00
lc_ctrl_jtag_errors 23.700s 8570.530us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.040s 162.374us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.290s 2164.605us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.990s 1263.505us 1 1 100.00
lc_ctrl_jtag_errors 23.700s 8570.530us 1 1 100.00
lc_ctrl_jtag_access 2.380s 193.363us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.290s 843.230us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.810s 182.474us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.220s 143.766us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.950s 5019.879us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.180s 2043.073us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.310s 17.593us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.440s 828.782us 1 1 100.00
lc_ctrl_jtag_alert_test 1.780s 348.707us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.900s 2427.005us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.050s 23.787us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.910s 10802.765us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.040s 26.304us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.870s 50.646us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.870s 50.646us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 14.935us 1 1 100.00
lc_ctrl_csr_rw 0.970s 13.654us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 16.912us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 28.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 14.935us 1 1 100.00
lc_ctrl_csr_rw 0.970s 13.654us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 16.912us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 28.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
lc_ctrl_tl_intg_err 2.090s 64.846us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.090s 64.846us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.050s 263.089us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.950s 221.852us 1 1 100.00
lc_ctrl_sec_cm 7.770s 898.899us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.780s 1484.456us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.700s 58.323us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.290s 2164.605us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.280s 312.152us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.280s 312.152us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.950s 905.553us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.930s 4452.055us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.930s 4452.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 52.460s 4750.798us 1 1 100.00