Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.02 %
  • code
  • 84.43 %
  • assert
  • 95.99 %
  • func
  • 92.63 %
  • line
  • 97.66 %
  • branch
  • 95.80 %
  • cond
  • 79.15 %
  • toggle
  • 85.92 %
  • FSM
  • 63.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.910s 162.207us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 57.661us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 59.679us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.990s 66.590us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 46.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 43.443us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 59.679us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 46.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.620s 77.595us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.050s 603.865us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 12.136us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.510s 150.058us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.140s 417.490us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_prog_failure 2.510s 150.058us 1 1 100.00
lc_ctrl_errors 5.140s 417.490us 1 1 100.00
lc_ctrl_security_escalation 3.760s 230.618us 1 1 100.00
lc_ctrl_jtag_state_failure 28.520s 2510.194us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.370s 1813.561us 1 1 100.00
lc_ctrl_jtag_errors 34.700s 3488.397us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.300s 1482.562us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.450s 3696.009us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.370s 1813.561us 1 1 100.00
lc_ctrl_jtag_errors 34.700s 3488.397us 1 1 100.00
lc_ctrl_jtag_access 6.570s 750.127us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.200s 1128.221us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.440s 195.085us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.210s 141.656us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.480s 1801.622us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.660s 3063.594us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.510s 43.145us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.370s 97.316us 1 1 100.00
lc_ctrl_jtag_alert_test 1.350s 120.691us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.660s 3052.361us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 26.712us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 96.730s 4694.589us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 28.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.780s 284.743us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.780s 284.743us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 57.661us 1 1 100.00
lc_ctrl_csr_rw 0.860s 59.679us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 46.917us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 25.182us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 57.661us 1 1 100.00
lc_ctrl_csr_rw 0.860s 59.679us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 46.917us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 25.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 72.467us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 72.467us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.050s 603.865us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.790s 239.367us 1 1 100.00
lc_ctrl_sec_cm 5.110s 668.116us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.760s 230.618us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.620s 77.595us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.450s 3696.009us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.700s 529.699us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.700s 529.699us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.980s 565.276us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.230s 397.724us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.230s 397.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.540s 710.849us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 111367876451055354039585565503626199198759197851986900936192195161814284887240 150
UVM_INFO @ 710848602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---