| V1 |
|
83.33% |
| V2 |
|
63.64% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 19.000s | 4990.056us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 32.243us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 68.078us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 301.104us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 65.214us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 10.768us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 68.078us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 65.214us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 7.000s | 946.986us | 0 | 1 | 0.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 2.000s | 65.154us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 20.000s | 4488.722us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 8.000s | 1341.615us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 48.886us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 25.883us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 21.114us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 21.114us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 32.243us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 68.078us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 65.214us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 23.272us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 32.243us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 68.078us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 65.214us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 23.272us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 267.734us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 14.096us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | 3 test runs | |||
| mbx_stress | 95771524105650923913720850217238690100538455145462932240520100305347148937766 | 291 |
UVM_INFO @ 946986407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_stress_zero_delays | 86971782901393627152764233048583724098993542395766278614594280936078009815691 | 89 |
UVM_INFO @ 65154454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_imbx_oob | 34719207104528084643685560257594658540923913480646101351602330971873320821957 | 202 |
UVM_INFO @ 4488721756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | 2 test runs | |||
| mbx_tl_errors | 13971959573865165549018468554816245720009198553108959717749421963489634422957 | 85 |
TL item was: req: (cip_tl_seq_item@17010) { a_addr: 'h24c9ab30 a_data: 'hf5fe1117 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'hab a_opcode: 'h1 a_user: 'h26922 d_param: 'h0 d_source: 'hab d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 21114462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_csr_mem_rw_with_rand_reset | 84195146904721031257037842202439170692657387747421905141920612673140167732352 | 86 |
TL item was: req: (cip_tl_seq_item@17451) { a_addr: 'h97fd0694 a_data: 'h2ccd27ac a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'he8 a_opcode: 'h1 a_user: 'h27896 d_param: 'h0 d_source: 'he8 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 10767848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|