| V1 |
|
100.00% |
| V2 |
|
85.71% |
| V2S |
|
88.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 44.367us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 42.823us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 3.000s | 15.563us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 7.000s | 123.766us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 3.000s | 15.754us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 4.000s | 41.174us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 3.000s | 15.563us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 15.754us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 102.000s | 12312.768us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 25.000s | 746.175us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 0 | 1 | 0.00 | |||
| otbn_reset | 11.000s | 20.345us | 0 | 1 | 0.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 46.000s | 133.965us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 37.000s | 168.838us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 49.000s | 167.107us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 7.000s | 14.177us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 0 | 1 | 0.00 | |||
| otbn_zero_state_err_urnd | 0.614s | 0.000us | 0 | 1 | 0.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 15.000s | 111.086us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 5.000s | 25.775us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 5.000s | 16.770us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 163.352us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 6.000s | 163.352us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 42.823us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 15.563us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 15.754us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 16.724us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 42.823us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 15.563us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 3.000s | 15.754us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 16.724us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 10.000s | 23.248us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 69.349us | 1 | 1 | 100.00 | |
| internal_integrity | 3 | 4 | 75.00 | |||
| otbn_alu_bignum_mod_err | 7.000s | 199.810us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 12.000s | 49.227us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 7.000s | 136.620us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 3.000s | 3.303us | 0 | 1 | 0.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 5.000s | 9.797us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 8.000s | 12.595us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 5.000s | 43.584us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 25.000s | 208.199us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 37.000s | 780.981us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 44.367us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 8.000s | 69.349us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 10.000s | 23.248us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 25.000s | 208.199us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 7.000s | 14.177us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 23.248us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 69.349us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 0.614s | 0.000us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 5.000s | 9.797us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 23.248us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 69.349us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 0.614s | 0.000us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 5.000s | 9.797us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 7.000s | 14.177us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 10.000s | 23.248us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 69.349us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 0.614s | 0.000us | 0 | 1 | 0.00 | |
| otbn_illegal_mem_acc | 5.000s | 9.797us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 6.000s | 42.069us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 8.000s | 86.116us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 0 | 1 | 0.00 | |||
| otbn_rnd_sec_cm | 0.675s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rnd_rng_digest | 0 | 1 | 0.00 | |||
| otbn_rnd_sec_cm | 0.675s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 7.000s | 17.357us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 9.000s | 58.881us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 10.000s | 101.901us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 10.000s | 101.901us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 12.000s | 89.149us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 37.000s | 168.838us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 9.000s | 43.882us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 15.000s | 53.686us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 152.000s | 984.040us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_stress_all_with_rand_reset | 225.000s | 1507.410us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 25.675us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 2 test runs | |||
| otbn_zero_state_err_urnd | 92296154818582861164863028471734281617250542037804038376872910617455152168522 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| otbn_rnd_sec_cm | 29847477640318450429878369116034696580770320824253558954149361311497673823699 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) | 1 test run | |||
| otbn_reset | 64098622781075114438468217514662572141127309023665922280501509145945980061236 | 121 |
UVM_ERROR @ 20345395 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
UVM_INFO @ 20345395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) | 1 test run | |||
| otbn_urnd_err | 6251744142836440832756555472950989180292868336954359470144381752221641594749 | 103 |
UVM_INFO @ 3303085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|