Simulation Results: otp_ctrl

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.42 %
  • code
  • 69.61 %
  • assert
  • 92.37 %
  • func
  • 46.27 %
  • line
  • 86.78 %
  • branch
  • 83.02 %
  • cond
  • 84.95 %
  • toggle
  • 60.16 %
  • FSM
  • 33.12 %
Validation stages
V1
88.89%
V2
50.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.890s 55.436us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.760s 128.447us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.660s 47.644us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.480s 905.957us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.000s 191.202us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.390s 34.842us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.660s 47.644us 1 1 100.00
otp_ctrl_csr_aliasing 5.000s 191.202us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.360s 94.842us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 82.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 104.600s 11847.398us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.070s 539.484us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 4.480s 301.967us 0 1 0.00
otp_ctrl_check_fail 4.060s 194.247us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.290s 135.313us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.590s 372.899us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.960s 2365.032us 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 2.810s 173.555us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.090s 66.709us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 13.970s 1563.046us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 77.670s 46237.257us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.420s 45.422us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.130s 75.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.900s 120.731us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.900s 120.731us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.760s 128.447us 1 1 100.00
otp_ctrl_csr_rw 1.660s 47.644us 1 1 100.00
otp_ctrl_csr_aliasing 5.000s 191.202us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.570s 187.408us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.760s 128.447us 1 1 100.00
otp_ctrl_csr_rw 1.660s 47.644us 1 1 100.00
otp_ctrl_csr_aliasing 5.000s 191.202us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.570s 187.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
otp_ctrl_tl_intg_err 12.810s 1567.248us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.810s 1567.248us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_macro_errs 2.090s 66.709us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_macro_errs 2.090s 66.709us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 1488.036us 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.070s 539.484us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.060s 194.247us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 17.530s 3653.490us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 279.600s 34966.017us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.290s 135.313us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.870s 638.512us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.090s 66.709us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 100.800s 46187.339us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 21.590s 3870.707us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 36381998942559310281667307775863147255506744570713926055841469620283648150426 3301
UVM_INFO @ 301967246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 49155503022147076104682907131258474222119872668875280209104282847679966322507 1522
UVM_INFO @ 173555229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 31966216144692265898465603797233720738405626156289999095359999931998059238908 956
UVM_INFO @ 372899082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64404908774568699207823151719516339641252112380203845676064600399748105076341 3236
UVM_INFO @ 3870706983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 86184769538736295040958510030209933815373754112029888839235131580556575183486 89
UVM_INFO @ 46187339440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 81424904116373916848481691183682410293967883600610935320204659091571569458181 90
UVM_INFO @ 46237257163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 1152533144686832837072976858885716110325408369453672541066214144435526653010 13219
UVM_INFO @ 3653490196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 27533339085625420412804936428097660222091955292589142273981302661201855229135 11611
UVM_INFO @ 1563046253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 38753091100316415615423427661463989488950143733211053895244676330763476709967 2687
UVM_INFO @ 194246506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 4472880946395229540418127979927525275931371178407107428233467848209345045015 652
UVM_INFO @ 66709130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 29337425634939872649182655006096111763267107597983706676247583888900111446927 115593
UVM_INFO @ 11847397535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 56548468760866902475219138588523982093868752916575935322718734190924950924130 3262
UVM_INFO @ 135312760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 28484077302150620045861162706998153838536158137072538778690709488728932620987 91
UVM_INFO @ 34842338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---