Simulation Results: rom_ctrl/32kb

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.89 %
  • code
  • 99.26 %
  • assert
  • 96.80 %
  • func
  • 97.61 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 99.49 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.290s 593.842us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.390s 175.057us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.450s 557.510us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.680s 133.716us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 555.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.470s 432.069us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.450s 557.510us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 555.704us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.030s 164.739us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.910s 794.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.900s 221.623us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.750s 1138.199us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.650s 312.480us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.310s 213.700us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.970s 554.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.970s 554.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.390s 175.057us 1 1 100.00
rom_ctrl_csr_rw 3.450s 557.510us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 555.704us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.740s 302.906us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.390s 175.057us 1 1 100.00
rom_ctrl_csr_rw 3.450s 557.510us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 555.704us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.740s 302.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.200s 418.708us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
rom_ctrl_tl_intg_err 42.070s 329.138us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.290s 593.842us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.290s 593.842us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.290s 593.842us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.070s 329.138us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
rom_ctrl_kmac_err_chk 7.650s 312.480us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 47.850s 5137.432us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.200s 418.708us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.040s 471.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 164.330s 4905.253us 1 1 100.00