Simulation Results: rom_ctrl/64kb

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 99.34 %
  • assert
  • 96.80 %
  • func
  • 93.79 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 97.77 %
  • toggle
  • 99.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.810s 770.278us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.720s 1074.086us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.580s 726.873us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.000s 1578.837us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.790s 1808.445us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.720s 297.105us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.580s 726.873us 1 1 100.00
rom_ctrl_csr_aliasing 6.790s 1808.445us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.520s 1160.722us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.280s 2391.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.760s 554.691us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 31.820s 1089.229us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.210s 548.188us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.410s 3327.400us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.380s 378.753us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.380s 378.753us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.720s 1074.086us 1 1 100.00
rom_ctrl_csr_rw 5.580s 726.873us 1 1 100.00
rom_ctrl_csr_aliasing 6.790s 1808.445us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.630s 1071.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.720s 1074.086us 1 1 100.00
rom_ctrl_csr_rw 5.580s 726.873us 1 1 100.00
rom_ctrl_csr_aliasing 6.790s 1808.445us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.630s 1071.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.500s 1155.203us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
rom_ctrl_tl_intg_err 93.800s 7621.230us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.810s 770.278us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.810s 770.278us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.810s 770.278us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 93.800s 7621.230us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
rom_ctrl_kmac_err_chk 14.210s 548.188us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 251.820s 8841.755us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.500s 1155.203us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 440.310s 1362.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 210.100s 13049.781us 1 1 100.00