Simulation Results: rstmgr

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.66 %
  • code
  • 99.16 %
  • assert
  • 97.44 %
  • func
  • 93.37 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.010s 63.572us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.020s 89.942us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.920s 65.461us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.290s 40.141us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.980s 67.160us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00
rstmgr_csr_aliasing 1.290s 40.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.840s 60.598us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.890s 41.637us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.050s 99.220us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.900s 732.885us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.900s 732.885us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.900s 732.885us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.900s 732.885us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.870s 701.059us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 39.927us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.190s 40.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.190s 40.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 89.942us 1 1 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00
rstmgr_csr_aliasing 1.290s 40.141us 1 1 100.00
rstmgr_same_csr_outstanding 1.110s 72.204us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 89.942us 1 1 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00
rstmgr_csr_aliasing 1.290s 40.141us 1 1 100.00
rstmgr_same_csr_outstanding 1.110s 72.204us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.990s 6866.264us 1 1 100.00
rstmgr_tl_intg_err 2.740s 380.249us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.990s 6866.264us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.990s 6866.264us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.740s 380.249us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.110s 60.121us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.540s 457.288us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.040s 292.252us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.990s 6866.264us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 36.555us 1 1 100.00