Simulation Results

Simulation Results: rv_dm/use_dmi_interface

07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.64 %

code
73.59 %

assert
94.93 %

func
67.39 %

line
90.22 %

branch
75.00 %

cond
76.32 %

toggle
70.15 %

FSM
56.25 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	2.190s	2042.888us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	0.800s	180.600us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.010s	158.352us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	3.080s	3132.593us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.160s	249.014us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	4.360s	1973.477us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	5.020s	2361.807us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	13.940s	6360.888us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	462.880s	257254.850us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.990s	1224.272us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	0.900s	155.806us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	0.910s	146.732us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.730s	159.929us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	2.030s	614.014us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	1.470s	503.730us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.900s	363.136us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	0.880s	451.394us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.990s	1224.272us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.750s	160.924us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	2.010s	746.911us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	0.910s	146.732us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.910s	130.610us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.850s	429.595us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.410s	207.934us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	19.230s	1433.266us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	17.040s	607.468us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.590s	172.454us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	17.040s	607.468us	1	1	100.00
	rv_dm_csr_rw	1.410s	207.934us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.660s	208.643us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.780s	142.446us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	2.190s	2042.888us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	2.160s	775.353us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.840s	143.533us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.940s	193.476us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.170s	1682.037us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	2.130s	842.878us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	0.810s	145.354us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	0.740s	211.566us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	0.780s	188.733us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.870s	450.065us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	4.020s	2009.925us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.580s	990.068us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.770s	60.993us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	2.150s	3821.123us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	75.290s	17623.931us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.830s	114.680us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	10800.107s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.830s	86.208us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.710s	815.355us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.710s	815.355us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	17.040s	607.468us	1	1	100.00
	rv_dm_csr_hw_reset	1.850s	429.595us	1	1	100.00
	rv_dm_csr_rw	1.410s	207.934us	1	1	100.00
	rv_dm_same_csr_outstanding	3.500s	517.877us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	17.040s	607.468us	1	1	100.00
	rv_dm_csr_hw_reset	1.850s	429.595us	1	1	100.00
	rv_dm_csr_rw	1.410s	207.934us	1	1	100.00
	rv_dm_same_csr_outstanding	3.500s	517.877us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	2.620s	1628.776us	1	1	100.00
	rv_dm_tl_intg_err	7.400s	2194.886us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	7.400s	2194.886us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.020s	2009.925us	1	1	100.00
	rv_dm_debug_disabled	0.810s	104.672us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.020s	2009.925us	1	1	100.00
	rv_dm_debug_disabled	0.810s	104.672us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	2.190s	2042.888us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	0.950s	109.359us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.720s	84.216us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.720s	84.216us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	0.950s	109.359us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	12.580s	2492.015us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	168.240s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
Error-[CNST-CIF] Constraints inconsistency failure				3 test runs
	rv_dm_delayed_resp_sba_tl_access	18230169035531265989795467707440521539838017173585263007823007555022531574417	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
	rv_dm_bad_sba_tl_access	49998534369911463281339172274204028094966873662882744062809608601623605476224	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
	rv_dm_autoincr_sba_tl_access	72840360580745023169883271537386327743805409124300018182240214189414437318081	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	28542754396305301194933383128469738663458049235784788009120288386921315409416	77	UVM_INFO @ 159928522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	28764860165097741481158044291623200898948643767253898426219338134141535942495	95	UVM_INFO @ 2492015162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	32999002020350717326631008623170011798000599530064738472563759806682905773673	86	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @5328
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	107313611851671574669571230423131350502388808659280236305127734191221225680428	77	UVM_INFO @ 60992607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	99768409588815554335703911807743901029801706493410529331997384512628517529833	77	UVM_INFO @ 450064531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	18608245635764796518994391161013638682719403645656113432115386449332549732982	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	19894897053441939007794019688273275900126014376361114530898329405314296916850	None