Simulation Results: rv_timer

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.25 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 97.94 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.760s 141.611us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 50.778us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.800s 54.469us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.230s 102.871us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.630s 66.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.920s 32.204us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.800s 54.469us 1 1 100.00
rv_timer_csr_aliasing 0.630s 66.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 85.413us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.340s 1791.557us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 303.570s 500916.912us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 303.570s 500916.912us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.190s 622.962us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 20.417us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.640s 47.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.940s 44.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.940s 44.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 50.778us 1 1 100.00
rv_timer_csr_rw 0.800s 54.469us 1 1 100.00
rv_timer_csr_aliasing 0.630s 66.922us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 33.823us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 50.778us 1 1 100.00
rv_timer_csr_rw 0.800s 54.469us 1 1 100.00
rv_timer_csr_aliasing 0.630s 66.922us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 33.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.810s 315.585us 1 1 100.00
rv_timer_tl_intg_err 1.020s 565.696us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.020s 565.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.810s 119.213us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 47.787us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 52.720s 26392.078us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 51851632974769764610321148071581916484598769008959192861558561209312587787531 77
UVM_INFO @ 119213291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 16590419406315151178792162354809362188763662352276396477733374555826129770090 77
UVM_INFO @ 85412828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 14050482295399886720021564835248035666084303404363594067132097576996015426317 75
UVM_INFO @ 47786566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---