Simulation Results: spi_host

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.09 %
  • code
  • 94.98 %
  • assert
  • 95.64 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 38.000s 11974.733us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 196.922us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 37.158us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 72.978us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 84.632us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 138.148us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 37.158us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.632us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 33.699us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 41.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 60.333us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 62.818us 1 1 100.00
spi_host_error_cmd 1.000s 84.557us 1 1 100.00
spi_host_event 7.000s 746.623us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 1234.717us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 1234.717us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 1234.717us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 321.415us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 35.142us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 1234.717us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 1234.717us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 38.000s 11974.733us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 38.000s 11974.733us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 6.000s 477.563us 1 1 100.00
spien 1 1 100.00
spi_host_spien 13.000s 498.143us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 12.000s 993.771us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 137.672us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 62.818us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 23.140us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 34.475us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 473.639us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 473.639us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 196.922us 1 1 100.00
spi_host_csr_rw 1.000s 37.158us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.632us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 71.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 196.922us 1 1 100.00
spi_host_csr_rw 1.000s 37.158us 1 1 100.00
spi_host_csr_aliasing 2.000s 84.632us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 71.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 92.246us 1 1 100.00
spi_host_sec_cm 1.000s 43.196us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 92.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 70.000s 4640.933us 1 1 100.00