Simulation Results: sram_ctrl/main

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.36 %
  • code
  • 96.83 %
  • assert
  • 96.46 %
  • func
  • 89.80 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 2911.735us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 23.410us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.451us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 569.846us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.811us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1735.946us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 21.451us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.811us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 98.000s 10524.673us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 3105.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 42.000s 26582.128us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 116.000s 6627.994us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 110.000s 5809.950us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 3957.692us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8951.649us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 39.000s 32112.678us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 733.712us 1 1 100.00
sram_ctrl_partial_access_b2b 92.000s 11303.612us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 7380.539us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2660.771us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2788.275us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3125.078us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1241.956us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 116.000s 32956.170us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 13.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 30.403us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 30.403us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.410us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.451us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.811us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 75.277us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.410us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.451us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.811us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 75.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7210.808us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 518.717us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 518.717us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3125.078us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3125.078us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.451us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 39.000s 32112.678us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 39.000s 32112.678us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 39.000s 32112.678us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8951.649us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 1390.017us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7210.808us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 2905.525us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2911.735us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2911.735us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 39.000s 32112.678us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 8951.649us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 2911.735us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 744.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 1640.085us 1 1 100.00