Simulation Results: uart

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.79 %
  • code
  • 96.68 %
  • assert
  • 97.12 %
  • func
  • 57.58 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.55 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.150s 479.028us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 16.478us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 27.876us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.230s 365.701us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 91.528us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.750s 25.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 27.876us 1 1 100.00
uart_csr_aliasing 0.820s 91.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 25.440s 134226.325us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.150s 479.028us 1 1 100.00
uart_tx_rx 25.440s 134226.325us 1 1 100.00
parity_error 2 2 100.00
uart_intr 2.680s 30120.675us 1 1 100.00
uart_rx_parity_err 14.040s 50726.323us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 25.440s 134226.325us 1 1 100.00
uart_intr 2.680s 30120.675us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 189.810s 186171.637us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 20.380s 17144.008us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 188.970s 121682.146us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 2.680s 30120.675us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 2.680s 30120.675us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 2.680s 30120.675us 1 1 100.00
perf 1 1 100.00
uart_perf 56.310s 1734.017us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 9.150s 6660.491us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.150s 6660.491us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.640s 720.305us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 17.540s 50633.266us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.100s 979.674us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 15.530s 5495.202us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 195.580s 59890.318us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 441.640s 218487.115us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.640s 14.549us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 22.571us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.880s 304.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.880s 304.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 16.478us 1 1 100.00
uart_csr_rw 0.730s 27.876us 1 1 100.00
uart_csr_aliasing 0.820s 91.528us 1 1 100.00
uart_same_csr_outstanding 0.740s 83.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 16.478us 1 1 100.00
uart_csr_rw 0.730s 27.876us 1 1 100.00
uart_csr_aliasing 0.820s 91.528us 1 1 100.00
uart_same_csr_outstanding 0.740s 83.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.930s 154.641us 1 1 100.00
uart_tl_intg_err 0.840s 128.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.840s 128.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.640s 2449.531us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 55337033140645997328508816108365686048795344459344804540204285821366281303905 74
UVM_ERROR @ 39689541 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 39689541 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR @ 71898905 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 71909322 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty