Simulation Results: ac_range_check

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 58.02 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
85.71%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 30.000s 1767.065us 1 1 100.00
ac_range_check_smoke_racl 0 1 0.00
ac_range_check_smoke_racl 40.000s 2172.886us 0 1 0.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 34.724us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 23.219us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 34.000s 2513.254us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 2129.053us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 150.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 23.219us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 2129.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 173.624us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 1259.829us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 150.000s 7611.468us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 14.727us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 16.760us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 44.893us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 44.893us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 34.724us 1 1 100.00
ac_range_check_csr_rw 2.000s 23.219us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 2129.053us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 210.551us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 34.724us 1 1 100.00
ac_range_check_csr_rw 2.000s 23.219us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 2129.053us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 210.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 2661.804us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 2661.804us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 2661.804us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 2661.804us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 66.000s 1462.445us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 12.058us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 183.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 230.000s 3632.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 30.000s 3161.992us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_smoke_racl 29035836413111511704786379124790940878706282724602639415216177908642000970192 4390
UVM_INFO @ 2172886440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---