Simulation Results: aes/gcm_masked

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.23 %
  • code
  • 95.52 %
  • assert
  • 98.57 %
  • func
  • 67.59 %
  • block
  • 96.30 %
  • line
  • 97.49 %
  • branch
  • 91.05 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 82.678us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 109.126us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 248.598us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 118.418us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 14452.831us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 97.461us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 91.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 118.418us 1 1 100.00
aes_csr_aliasing 4.000s 97.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 109.126us 1 1 100.00
aes_config_error 2.000s 180.394us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 109.126us 1 1 100.00
aes_config_error 2.000s 180.394us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
back2back 2 2 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_b2b 12.000s 397.947us 1 1 100.00
backpressure 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 109.126us 1 1 100.00
aes_config_error 2.000s 180.394us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 73.274us 1 1 100.00
aes_config_error 2.000s 180.394us 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 186.902us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 1095.535us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 712.740us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
stress 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_sideload 4.000s 268.890us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 168.601us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 4.000s 169.672us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 172.753us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 127.258us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 88.083us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 88.083us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 248.598us 1 1 100.00
aes_csr_rw 2.000s 118.418us 1 1 100.00
aes_csr_aliasing 4.000s 97.461us 1 1 100.00
aes_same_csr_outstanding 2.000s 163.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 248.598us 1 1 100.00
aes_csr_rw 2.000s 118.418us 1 1 100.00
aes_csr_aliasing 4.000s 97.461us 1 1 100.00
aes_same_csr_outstanding 2.000s 163.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 28.000s 2315.909us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 325.998us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 7.000s 704.408us 1 1 100.00
aes_tl_intg_err 2.000s 363.854us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 363.854us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 109.126us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
aes_core_fi 3.000s 174.043us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 172.753us 1 1 100.00
aes_config_error 2.000s 180.394us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_core_fi 3.000s 174.043us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 561.769us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 67.718us 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 120.140us 1 1 100.00
aes_sideload 4.000s 268.890us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.718us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.718us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 67.718us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 67.718us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 67.718us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 120.140us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 185.556us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 185.556us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 185.556us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 185.556us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 145.113us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 1.000s 51.063us 1 1 100.00
aes_fi 3.000s 185.556us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 185.556us 1 1 100.00
aes_control_fi 2.000s 58.536us 1 1 100.00
aes_cipher_fi 17.000s 10015.631us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 2034.432us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 25734693249982942783720754742518041692367609116984724344697299084134141746033 146
UVM_INFO @ 10015631003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 98271864909475426509909093115585735210683445854163271655182541904603940419648 541
UVM_INFO @ 2034431848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---