Simulation Results: aes/gcm_unmasked

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.02 %
  • code
  • 90.34 %
  • assert
  • 97.75 %
  • func
  • 66.98 %
  • block
  • 90.32 %
  • line
  • 92.48 %
  • branch
  • 82.25 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 65.157us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 106.183us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 94.376us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 59.195us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 785.502us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 126.034us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 73.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 59.195us 1 1 100.00
aes_csr_aliasing 2.000s 126.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 106.183us 1 1 100.00
aes_config_error 2.000s 182.311us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 106.183us 1 1 100.00
aes_config_error 2.000s 182.311us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_b2b 6.000s 136.824us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 106.183us 1 1 100.00
aes_config_error 2.000s 182.311us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 80.599us 1 1 100.00
aes_config_error 2.000s 182.311us 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 113.026us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 602.912us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_sideload 2.000s 165.538us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 232.792us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 13.000s 4808.757us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 71.541us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 366.733us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 366.733us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.376us 1 1 100.00
aes_csr_rw 1.000s 59.195us 1 1 100.00
aes_csr_aliasing 2.000s 126.034us 1 1 100.00
aes_same_csr_outstanding 2.000s 439.999us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.376us 1 1 100.00
aes_csr_rw 1.000s 59.195us 1 1 100.00
aes_csr_aliasing 2.000s 126.034us 1 1 100.00
aes_same_csr_outstanding 2.000s 439.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 98.631us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 132.231us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 592.081us 1 1 100.00
aes_tl_intg_err 3.000s 540.152us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 540.152us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 106.183us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
aes_core_fi 2.000s 66.349us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 182.311us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_core_fi 2.000s 66.349us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 305.482us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 63.480us 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 152.995us 1 1 100.00
aes_sideload 2.000s 165.538us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.480us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.480us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 63.480us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 63.480us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 63.480us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 152.995us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 529.132us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 529.132us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 529.132us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 529.132us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 121.387us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_ctr_fi 2.000s 74.963us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 2.000s 529.132us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 2.000s 529.132us 1 1 100.00
aes_control_fi 2.000s 83.847us 1 1 100.00
aes_cipher_fi 2.000s 89.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 2095.032us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '*' in file '/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_*/aes_scoreboard.sv' at time * PS + *. 1 test run
aes_stress_all 80463521731415879874773450766489863466907046985664595229909167240800599036660 16596
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 1267339608 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 1267339608 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 1267339608 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 1267339608 PS + 10.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 101105203540519186109368318027418931043430333787150408711323122989172792895724 2027
UVM_INFO @ 2095031595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---