Simulation Results: alert_handler

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.87 %
  • code
  • 89.72 %
  • assert
  • 98.11 %
  • func
  • 75.77 %
  • line
  • 99.71 %
  • branch
  • 98.15 %
  • cond
  • 90.62 %
  • toggle
  • 84.29 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 9.180s 164.458us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.060s 268.622us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 101.740s 3855.914us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 146.270s 1513.720us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.310s 66.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.060s 268.622us 1 1 100.00
alert_handler_csr_aliasing 146.270s 1513.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 115.720s 7993.730us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 60.910s 2846.576us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 779.390s 46384.057us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 16.530s 764.098us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 9.030s 195.925us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 18.460s 267.625us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 267.830s 19281.017us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1732.450s 39861.058us 1 1 100.00
alert_handler_lpg_stub_clk 519.420s 78156.136us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 47.460s 3039.724us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.020s 918.309us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.830s 35.594us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.380s 19.278us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.190s 237.596us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.190s 237.596us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 9.180s 164.458us 1 1 100.00
alert_handler_csr_rw 5.060s 268.622us 1 1 100.00
alert_handler_csr_aliasing 146.270s 1513.720us 1 1 100.00
alert_handler_same_csr_outstanding 31.180s 1417.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 9.180s 164.458us 1 1 100.00
alert_handler_csr_rw 5.060s 268.622us 1 1 100.00
alert_handler_csr_aliasing 146.270s 1513.720us 1 1 100.00
alert_handler_same_csr_outstanding 31.180s 1417.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 129.710s 2871.284us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 129.710s 2871.284us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 129.710s 2871.284us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 129.710s 2871.284us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 540.500s 5604.319us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
alert_handler_tl_intg_err 3.910s 184.253us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.910s 184.253us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 129.710s 2871.284us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 28.600s 714.254us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.530s 764.098us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1732.450s 39861.058us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.530s 764.098us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 779.390s 46384.057us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 779.390s 46384.057us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.480s 572.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 110.620s 7016.916us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 100396708897193890447822523021195771403912626566210468046248125405084538451065 162
UVM_INFO @ 918309023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
alert_handler_stress_all_with_rand_reset 19641567559412847682087681214290955981638793689850642756445175877244147425837 213
UVM_INFO @ 7016915958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---