Simulation Results: clkmgr

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.98 %
  • code
  • 67.59 %
  • assert
  • 88.64 %
  • func
  • 44.72 %
  • line
  • 81.41 %
  • branch
  • 86.30 %
  • cond
  • 75.24 %
  • toggle
  • 95.00 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.340s 76.954us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.030s 58.224us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.290s 27.033us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.780s 5.706us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.980s 10.124us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
clkmgr_csr_aliasing 0.780s 5.706us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.820s 32.210us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.260s 39.115us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.980s 24.331us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.340s 76.954us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.780s 5.898us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.630s 4.269us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.780s 5.898us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.880s 34.323us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.070s 45.755us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.770s 56.460us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.770s 56.460us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.030s 58.224us 1 1 100.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
clkmgr_csr_aliasing 0.780s 5.706us 0 1 0.00
clkmgr_same_csr_outstanding 0.630s 3.173us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.030s 58.224us 1 1 100.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
clkmgr_csr_aliasing 0.780s 5.706us 0 1 0.00
clkmgr_same_csr_outstanding 0.630s 3.173us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.910s 21.973us 0 1 0.00
clkmgr_tl_intg_err 0.700s 4.093us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 0.900s 31.293us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 0.900s 31.293us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 0.900s 31.293us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 0.900s 31.293us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.800s 7.839us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.700s 4.093us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.780s 5.898us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.630s 4.269us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 0.900s 31.293us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.000s 38.683us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.910s 21.973us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.680s 5.323us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.910s 21.973us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.580s 2.445us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.610s 2.722us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 24940429233324780188862877108693889363366458023710925126619484602559069302149 75
UVM_INFO @ 7838534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 27245532188814702226970210504870757316399174128870522742310443084192041687616 89
UVM_INFO @ 4093223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 11658893847917272857460904673838619332077491821016132506555321389143931014249 76
UVM_INFO @ 5706470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 109849788948011737751606285617957550728434213049491364647472394511360875260272 76
UVM_INFO @ 10124329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 35085947254227206180908823120299778500198688024209386635111463240332152983803 76
UVM_INFO @ 5898100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 71065772961400904066902224504117628649133660701970830539835175260307292770221 76
UVM_INFO @ 34323178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 93811700140987545771175075622009771042943197126056793741721663908255690146593 78
UVM_INFO @ 4269487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 413749411336518181268138580468017715123053773868182378279590437218261389030 79
UVM_INFO @ 2721590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 75884986691396798980183273239145156645736906076154284048605597749505334679703 74
UVM_INFO @ 2444504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 45346545953836317412064797328097817913635176781043196662629232427472702654614 80
UVM_INFO @ 21973027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_rw 98009125214378188463071988495836106822859646262966273713526750942308071814540 75
UVM_INFO @ 5323460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 95562740503656841784578634340951706505003732076449288490458937112452150695393 75
UVM_INFO @ 27032907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 97439058837146533634452227088129978256319566935849030423845538190488026991637 75
UVM_INFO @ 3172862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---