Simulation Results: dma

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.67 %
  • code
  • 91.85 %
  • assert
  • 95.97 %
  • func
  • 63.20 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1288.989us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 431.607us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 680.104us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 21.398us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 29.191us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 1072.522us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 1359.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 46.356us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 29.191us 1 1 100.00
dma_csr_aliasing 4.000s 1359.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 122.000s 29788.631us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 218.000s 44769.954us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 134.000s 11269.888us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 134.000s 11269.888us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 218.000s 44769.954us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 129.000s 10365.903us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 134.000s 11269.888us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 16.000s 1538.239us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 117.000s 22955.390us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 17.299us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 40.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 146.629us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 146.629us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 21.398us 1 1 100.00
dma_csr_rw 1.000s 29.191us 1 1 100.00
dma_csr_aliasing 4.000s 1359.363us 1 1 100.00
dma_same_csr_outstanding 2.000s 134.637us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 21.398us 1 1 100.00
dma_csr_rw 1.000s 29.191us 1 1 100.00
dma_csr_aliasing 4.000s 1359.363us 1 1 100.00
dma_same_csr_outstanding 2.000s 134.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 770.096us 1 1 100.00
dma_generic_stress 129.000s 10365.903us 1 1 100.00
dma_handshake_stress 134.000s 11269.888us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 331.578us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 404.091us 1 1 100.00
dma_sec_cm 1.000s 11.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 146.000s 64388.248us 1 1 100.00
dma_longer_transfer 3.000s 126.146us 1 1 100.00
dma_stress_all_with_rand_reset 10.000s 2884.460us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 11422997929679249402585049054016277553037891765339471648620719154887701857101 106
UVM_INFO @ 2884460132ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---