Simulation Results: edn/edn0

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.48 %
  • code
  • 84.21 %
  • assert
  • 94.25 %
  • func
  • 47.97 %
  • block
  • 93.86 %
  • line
  • 96.83 %
  • branch
  • 86.85 %
  • toggle
  • 73.32 %
  • FSM
  • 79.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 49.763us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 144.572us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 39.487us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 251.891us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 74.056us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 67.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 39.487us 1 1 100.00
edn_csr_aliasing 2.000s 74.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 81.010us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 81.010us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 81.010us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 20.509us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 40.787us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 59.944us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 39.914us 1 1 100.00
edn_disable_auto_req_mode 2.000s 41.292us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.000s 307.934us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 58.642us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 19.385us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 27.189us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 27.189us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 144.572us 1 1 100.00
edn_csr_rw 2.000s 39.487us 1 1 100.00
edn_csr_aliasing 2.000s 74.056us 1 1 100.00
edn_same_csr_outstanding 1.000s 23.609us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 144.572us 1 1 100.00
edn_csr_rw 2.000s 39.487us 1 1 100.00
edn_csr_aliasing 2.000s 74.056us 1 1 100.00
edn_same_csr_outstanding 1.000s 23.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
edn_tl_intg_err 3.000s 179.134us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 39.671us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 40.787us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 40.787us 1 1 100.00
edn_sec_cm 4.000s 491.286us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 40.787us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 179.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 38.000s 13514.838us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 14239273376096507063902923193623581894169736437672176402333810823517415163847 151
UVM_INFO @ 13514838333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---