Simulation Results: hmac

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.52 %
  • code
  • 95.85 %
  • assert
  • 95.86 %
  • func
  • 28.85 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.53 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 5.000s 223.797us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 190.167us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 18.457us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 1223.964us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 2083.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 69.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 18.457us 1 1 100.00
hmac_csr_aliasing 6.000s 2083.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 64.000s 12028.602us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.000s 961.293us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 11.000s 172.352us 1 1 100.00
hmac_test_sha384_vectors 24.000s 234.703us 1 1 100.00
hmac_test_sha512_vectors 23.000s 793.806us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 309.790us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 450.969us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 297.653us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 20.000s 2679.667us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 45.000s 3753.549us 1 1 100.00
error 1 1 100.00
hmac_error 51.000s 4728.371us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 78.000s 15432.139us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 5.000s 223.797us 1 1 100.00
hmac_long_msg 64.000s 12028.602us 1 1 100.00
hmac_back_pressure 44.000s 961.293us 1 1 100.00
hmac_datapath_stress 45.000s 3753.549us 1 1 100.00
hmac_burst_wr 20.000s 2679.667us 1 1 100.00
hmac_stress_all 149.000s 44576.004us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 5.000s 223.797us 1 1 100.00
hmac_long_msg 64.000s 12028.602us 1 1 100.00
hmac_back_pressure 44.000s 961.293us 1 1 100.00
hmac_datapath_stress 45.000s 3753.549us 1 1 100.00
hmac_wipe_secret 78.000s 15432.139us 1 1 100.00
hmac_test_sha256_vectors 11.000s 172.352us 1 1 100.00
hmac_test_sha384_vectors 24.000s 234.703us 1 1 100.00
hmac_test_sha512_vectors 23.000s 793.806us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 309.790us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 450.969us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 297.653us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 5.000s 223.797us 1 1 100.00
hmac_long_msg 64.000s 12028.602us 1 1 100.00
hmac_back_pressure 44.000s 961.293us 1 1 100.00
hmac_datapath_stress 45.000s 3753.549us 1 1 100.00
hmac_burst_wr 20.000s 2679.667us 1 1 100.00
hmac_error 51.000s 4728.371us 1 1 100.00
hmac_wipe_secret 78.000s 15432.139us 1 1 100.00
hmac_test_sha256_vectors 11.000s 172.352us 1 1 100.00
hmac_test_sha384_vectors 24.000s 234.703us 1 1 100.00
hmac_test_sha512_vectors 23.000s 793.806us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 309.790us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 450.969us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 297.653us 1 1 100.00
hmac_stress_all 149.000s 44576.004us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 149.000s 44576.004us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 18.744us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 40.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 300.817us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 300.817us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 190.167us 1 1 100.00
hmac_csr_rw 2.000s 18.457us 1 1 100.00
hmac_csr_aliasing 6.000s 2083.937us 1 1 100.00
hmac_same_csr_outstanding 2.000s 142.401us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 190.167us 1 1 100.00
hmac_csr_rw 2.000s 18.457us 1 1 100.00
hmac_csr_aliasing 6.000s 2083.937us 1 1 100.00
hmac_same_csr_outstanding 2.000s 142.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 696.845us 1 1 100.00
hmac_tl_intg_err 3.000s 101.024us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 101.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 5.000s 223.797us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 45.859us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 35.000s 12293.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 26.120us 1 1 100.00