Simulation Results

Simulation Results: i2c

11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.40 %

code
89.98 %

assert
96.19 %

func
82.04 %

block
96.12 %

line
95.62 %

branch
93.04 %

toggle
87.10 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	29.000s	2959.524us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.000s	761.918us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	22.818us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	47.314us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2080.117us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	133.198us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	41.882us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	47.314us	1	1	100.00
	i2c_csr_aliasing	3.000s	133.198us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	3.000s	226.099us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	633.000s	4606.466us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	27.983us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.148s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1315.000s	46814.079us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	223.934us	1	1	100.00
	i2c_host_fifo_fmt_empty	18.000s	804.209us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	134.161us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	167.000s	10708.424us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	2515.714us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	27.375us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	2058.992us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	792.684us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	22.000s	1715.574us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1636.534us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	539.237us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	254.753us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	4.000s	17164.335us	1	1	100.00
	i2c_target_stress_rd	22.000s	1715.574us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	3071.158us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.000s	2664.431us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	954.760us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	14.000s	10009.250us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	743.905us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	116.599us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	633.000s	4606.466us	1	1	100.00
	i2c_host_perf_precise	80.000s	2579.045us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	2515.714us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.000s	492.000us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	2525.105us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	1150.253us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	146.932us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	16.000s	1895.283us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	993.495us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	14.647us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	18.272us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	58.150us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	58.150us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.818us	1	1	100.00
	i2c_csr_rw	1.000s	47.314us	1	1	100.00
	i2c_csr_aliasing	3.000s	133.198us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	112.590us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.818us	1	1	100.00
	i2c_csr_rw	1.000s	47.314us	1	1	100.00
	i2c_csr_aliasing	3.000s	133.198us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	112.590us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	145.963us	1	1	100.00
	i2c_sec_cm	2.000s	75.301us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	145.963us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.000s	281.667us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	22.388us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	27.000s	3865.041us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	i2c_host_fifo_watermark	63207076318461332128181157987768134721921846576543745571426865773554963178146	None
	i2c_host_stress_all	84138362446664684501064074707192673578557602605257892062157761564991371444750	None
	i2c_target_intr_stress_wr	50701395466839212010883685130182701492360728678896632149381679549206938814181	None
	i2c_target_stress_all	47646249216543409944331655648716314310738979768372950513354409231531140225449	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	75335794077214787608236513400626437787474787709266362026193485904753839696892	89	UVM_INFO @ 226099147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	49099311146918488602926820385960940129700119524294793085639097382696693199946	122	UVM_INFO @ 3865040999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	92643782483572798666264932184505715999146634269396212181187432874191183393440	93	UVM_INFO @ 2058991634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	109196479471335735853224329094137764196227635708020052830303298646395092466641	87	UVM_INFO @ 22388177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	13678812662324404736684376839951746143874430474088215893869001882378446486885	88	UVM_INFO @ 10009250075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	76383171322740711935887302003928046536764393318628139295518416419602473903846	94	UVM_INFO @ 281666673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	13607851252371942660474475480565962588917798023954882854058036774210765615113	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------