Simulation Results: kmac/masked

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.59 %
  • code
  • 90.67 %
  • assert
  • 97.98 %
  • func
  • 95.13 %
  • line
  • 98.87 %
  • branch
  • 96.11 %
  • cond
  • 91.59 %
  • toggle
  • 99.89 %
  • FSM
  • 66.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 33.470s 3367.805us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.160s 31.387us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.140s 53.153us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.190s 1174.200us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.610s 2004.522us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.090s 25.898us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.140s 53.153us 1 1 100.00
kmac_csr_aliasing 7.610s 2004.522us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.990s 13.412us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.360s 56.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 427.730s 72664.532us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 594.460s 92537.498us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 31.920s 2606.160us 1 1 100.00
kmac_test_vectors_sha3_256 1428.670s 61076.299us 1 1 100.00
kmac_test_vectors_sha3_384 1398.600s 73843.956us 1 1 100.00
kmac_test_vectors_sha3_512 1081.980s 198930.319us 1 1 100.00
kmac_test_vectors_shake_128 190.860s 57478.386us 1 1 100.00
kmac_test_vectors_shake_256 1437.490s 69636.663us 1 1 100.00
kmac_test_vectors_kmac 2.840s 125.739us 1 1 100.00
kmac_test_vectors_kmac_xof 3.620s 850.438us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 245.870s 19474.368us 1 1 100.00
app 1 1 100.00
kmac_app 121.650s 3171.143us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 61.450s 3368.516us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 84.570s 5769.189us 1 1 100.00
error 1 1 100.00
kmac_error 362.760s 22345.661us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.610s 1205.111us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 3.290s 353.699us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.180s 27.851us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.800s 30.007us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 53.780s 26158.573us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.750s 196.384us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 129.150s 3913.601us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.940s 13.938us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.000s 18.903us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.870s 161.058us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.870s 161.058us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.160s 31.387us 1 1 100.00
kmac_csr_rw 1.140s 53.153us 1 1 100.00
kmac_csr_aliasing 7.610s 2004.522us 1 1 100.00
kmac_same_csr_outstanding 2.360s 46.299us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.160s 31.387us 1 1 100.00
kmac_csr_rw 1.140s 53.153us 1 1 100.00
kmac_csr_aliasing 7.610s 2004.522us 1 1 100.00
kmac_same_csr_outstanding 2.360s 46.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 25.525us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.430s 25.525us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 25.525us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.430s 25.525us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.750s 1616.432us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 43.140s 5549.166us 1 1 100.00
kmac_tl_intg_err 4.580s 512.713us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.580s 512.713us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.750s 196.384us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 33.470s 3367.805us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 245.870s 19474.368us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.430s 25.525us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 43.140s 5549.166us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 43.140s 5549.166us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 43.140s 5549.166us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 33.470s 3367.805us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.750s 196.384us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 43.140s 5549.166us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 261.330s 28288.818us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 33.470s 3367.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 56.950s 9203.332us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 107217548136252195553242887261125424569850213282208169636922038391409430203790 333
UVM_INFO @ 9203331888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---