Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.57 %
  • code
  • 92.75 %
  • assert
  • 95.97 %
  • func
  • 85.99 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 87.07 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 88.502us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 3.000s 17.390us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.673us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 221.466us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 25.711us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 27.382us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 43.673us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 25.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 288.550us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 301.194us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.146us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 4.000s 293.683us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 1146.186us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_prog_failure 4.000s 293.683us 1 1 100.00
lc_ctrl_errors 6.000s 1146.186us 1 1 100.00
lc_ctrl_security_escalation 5.000s 405.814us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 1320.407us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 205.701us 1 1 100.00
lc_ctrl_jtag_errors 29.000s 7521.260us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 192.890us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 1161.332us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 205.701us 1 1 100.00
lc_ctrl_jtag_errors 29.000s 7521.260us 1 1 100.00
lc_ctrl_jtag_access 6.000s 1818.652us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.000s 1243.777us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 1116.418us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.000s 218.271us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 2025.055us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 482.707us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 20.044us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 189.696us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 284.745us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 804.072us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 21.305us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 16.000s 952.265us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 3.000s 65.549us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 224.437us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 224.437us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 3.000s 17.390us 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.673us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 25.711us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 24.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 3.000s 17.390us 1 1 100.00
lc_ctrl_csr_rw 2.000s 43.673us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 25.711us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 24.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 930.495us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 930.495us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 301.194us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 448.117us 1 1 100.00
lc_ctrl_sec_cm 3.000s 237.925us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 405.814us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 288.550us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 1161.332us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 2497.251us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 2497.251us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 583.660us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.000s 1481.140us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.000s 1481.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.000s 2053.813us 1 1 100.00