Simulation Results: lc_ctrl/volatile_unlock_enabled

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.93 %
  • code
  • 93.51 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 97.11 %
  • line
  • 97.66 %
  • branch
  • 92.68 %
  • toggle
  • 88.47 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 18.923us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 21.730us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.555us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 237.673us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.481us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 27.603us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 25.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 317.544us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 2124.632us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.198us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 30.167us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1325.858us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_prog_failure 2.000s 30.167us 1 1 100.00
lc_ctrl_errors 5.000s 1325.858us 1 1 100.00
lc_ctrl_security_escalation 5.000s 642.996us 1 1 100.00
lc_ctrl_jtag_state_failure 19.000s 2227.724us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 3837.620us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 2972.803us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 159.945us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1260.193us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 3837.620us 1 1 100.00
lc_ctrl_jtag_errors 26.000s 2972.803us 1 1 100.00
lc_ctrl_jtag_access 18.000s 1052.686us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 7040.044us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 555.366us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 43.142us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 3102.064us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 554.667us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 23.385us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 232.189us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 92.700us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 16.000s 5016.343us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 46.955us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 15.000s 1768.984us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 35.192us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 91.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 91.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 21.730us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.481us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 39.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 21.730us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.555us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 71.481us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 39.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
lc_ctrl_tl_intg_err 5.000s 172.234us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 5.000s 172.234us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 2124.632us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 545.247us 1 1 100.00
lc_ctrl_sec_cm 4.000s 445.868us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 642.996us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 317.544us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1260.193us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2521.444us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2521.444us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 770.454us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.000s 425.626us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.000s 425.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 2231.849us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 75880463323099100060396494605328505158210205497887845333047045475608801769543 190
UVM_INFO @ 2231848701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---