Simulation Results: mbx

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.86 %
  • code
  • 91.41 %
  • assert
  • 96.96 %
  • func
  • 78.21 %
  • block
  • 96.82 %
  • line
  • 96.64 %
  • branch
  • 91.71 %
  • toggle
  • 85.88 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 42.000s 2246.384us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 111.250us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 22.662us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 39.383us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 64.223us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 1.047us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 22.662us 1 1 100.00
mbx_csr_aliasing 2.000s 64.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 40.000s 2148.909us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 193.971us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 37.000s 21013.378us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 18.000s 1096.430us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 28.752us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 14.655us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.947us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.947us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 111.250us 1 1 100.00
mbx_csr_rw 2.000s 22.662us 1 1 100.00
mbx_csr_aliasing 2.000s 64.223us 1 1 100.00
mbx_same_csr_outstanding 1.000s 21.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 111.250us 1 1 100.00
mbx_csr_rw 2.000s 22.662us 1 1 100.00
mbx_csr_aliasing 2.000s 64.223us 1 1 100.00
mbx_same_csr_outstanding 1.000s 21.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 251.601us 1 1 100.00
mbx_sec_cm 1.000s 26.191us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 91657115618392168216801335694170177817395133075577975141965529622818092052666 85
TL item was: req: (cip_tl_seq_item@19149) { a_addr: 'h3d814e10 a_data: 'h47268e02 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'h13 a_opcode: 'h1 a_user: 'h25b2f d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3947358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 16854040827735495326913872494003158078034763527749098740510342618517520112154 86
TL item was: req: (cip_tl_seq_item@20908) { a_addr: 'h6cf51ab4 a_data: 'hfe89c78d a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'hac a_opcode: 'h1 a_user: 'h26d0c d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1046811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 63213025463302927787182367686171845234695907181516521191537031432868052105226 177
UVM_INFO @ 193970754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---