Simulation Results: otp_ctrl

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.52 %
  • code
  • 69.53 %
  • assert
  • 90.57 %
  • func
  • 48.46 %
  • line
  • 87.13 %
  • branch
  • 81.90 %
  • cond
  • 84.37 %
  • toggle
  • 57.77 %
  • FSM
  • 36.47 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.550s 56.702us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.590s 210.038us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.260s 77.844us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.370s 1553.698us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 9.160s 579.976us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.310s 2004.108us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.260s 77.844us 1 1 100.00
otp_ctrl_csr_aliasing 9.160s 579.976us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.010s 152.770us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.400s 45.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 102.150s 4922.521us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.580s 215.798us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 10.890s 840.513us 1 1 100.00
otp_ctrl_check_fail 2.960s 79.335us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.600s 442.083us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 3.400s 260.878us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 13.860s 1011.729us 0 1 0.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.180s 429.484us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 13.510s 1382.644us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 2.580s 260.091us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 11.710s 821.294us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.540s 84.801us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.660s 174.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.450s 165.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.450s 165.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 210.038us 1 1 100.00
otp_ctrl_csr_rw 2.260s 77.844us 1 1 100.00
otp_ctrl_csr_aliasing 9.160s 579.976us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.070s 56.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 210.038us 1 1 100.00
otp_ctrl_csr_rw 2.260s 77.844us 1 1 100.00
otp_ctrl_csr_aliasing 9.160s 579.976us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.070s 56.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 12.910s 793.445us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.910s 793.445us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_macro_errs 13.510s 1382.644us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_macro_errs 13.510s 1382.644us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.190s 194.558us 1 1 100.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.580s 215.798us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.960s 79.335us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 5.460s 1892.462us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 333.770s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.600s 442.083us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.080s 2629.995us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 13.510s 1382.644us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 56.330s 21877.296us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 4.930s 212.487us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 5 test runs
otp_ctrl_parallel_lc_req 69894889082621700582772072032375925847679160867207213001369196001759728971934 14665
UVM_INFO @ 1011729292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 28102995408412193949013514785416271201444264609052266080381814116035919293305 5238
UVM_INFO @ 1892462475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 7379636704675236128019599873845164424665315816886014527756372867776202914759 12894
UVM_INFO @ 1382644276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 67612160276734512217863117380094190765971905887566514553427353716661884379657 2263
UVM_INFO @ 260878492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 80748425528396358571675904575774361912491778928068400007803874292048215559456 1676
UVM_INFO @ 260090949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 80261377745008003857059417302186157158686245092750715435610573468637080736199 120559
UVM_INFO @ 4922520679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 30899420934895899090571707301913126153864843281921443142724326491752454958821 89
UVM_INFO @ 21877296295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 58996377990045350459635874030164310079205817907305931436884366486067483148471 2212
UVM_INFO @ 79335247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 106795666927524377549204013435232921448585641840245677011411125427571499014036 1455
UVM_INFO @ 212487376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_stress_all 30994985442061708144902419585241830156428136239079546068900541078175878795363 5544
UVM_INFO @ 821294169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 57755803606767641446780113414869569059692980005250127076218395459704941966667 2879
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---