Simulation Results: rom_ctrl/32kb

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.45 %
  • code
  • 94.09 %
  • assert
  • 96.79 %
  • func
  • 92.47 %
  • block
  • 95.61 %
  • line
  • 96.00 %
  • branch
  • 93.55 %
  • toggle
  • 86.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 594.899us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 130.636us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 176.484us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 2036.741us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 166.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 604.495us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 176.484us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 166.994us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 129.780us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 292.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 180.727us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.000s 3630.546us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 454.790us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 212.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 164.581us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 164.581us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 130.636us 1 1 100.00
rom_ctrl_csr_rw 3.000s 176.484us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 166.994us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 131.208us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 130.636us 1 1 100.00
rom_ctrl_csr_rw 3.000s 176.484us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 166.994us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 131.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2202.064us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
rom_ctrl_tl_intg_err 13.000s 348.637us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 594.899us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 594.899us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 594.899us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 13.000s 348.637us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 454.790us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 61.000s 38047.516us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2202.064us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 49.000s 2524.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 50.000s 9971.384us 1 1 100.00