Simulation Results: rstmgr

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 99.21 %
  • assert
  • 97.44 %
  • func
  • 94.28 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.110s 61.453us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.070s 90.334us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 1.880s 50.763us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.420s 55.370us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.310s 94.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00
rstmgr_csr_aliasing 1.420s 55.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.360s 70.999us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.250s 42.590us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.100s 48.165us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.060s 492.141us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.060s 492.141us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.060s 492.141us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.060s 492.141us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.140s 86.357us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.760s 35.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.870s 58.479us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.870s 58.479us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 90.334us 1 1 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00
rstmgr_csr_aliasing 1.420s 55.370us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 40.210us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 90.334us 1 1 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00
rstmgr_csr_aliasing 1.420s 55.370us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 40.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.150s 3548.609us 1 1 100.00
rstmgr_tl_intg_err 4.020s 625.144us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.150s 3548.609us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.150s 3548.609us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.020s 625.144us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.160s 55.633us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.760s 459.806us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.010s 291.813us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.150s 3548.609us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 37.121us 1 1 100.00