Simulation Results

Simulation Results: rv_dm/use_dmi_interface

11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.74 %

code
74.78 %

assert
96.20 %

func
92.24 %

block
89.75 %

line
89.52 %

branch
72.17 %

toggle
74.95 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		65.22%
V2S		85.71%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				0	1	0.00
	rv_dm_smoke	30.000s	204.710us	0	1	0.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	30.000s	196.475us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	184.582us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	36.000s	11281.693us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	517.713us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	37.000s	2748.227us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	43.000s	16709.495us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	40.000s	9824.416us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	62.000s	35033.005us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	185.106us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	245.032us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	561.986us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	157.763us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	382.764us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	30.000s	1191.545us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	33.000s	100.217us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	1305.231us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	185.106us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	344.602us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	34.000s	796.363us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	561.986us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	92.252us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	337.909us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	32.000s	53.358us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	84.000s	56252.783us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	65.000s	18079.173us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	170.396us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	65.000s	18079.173us	1	1	100.00
	rv_dm_csr_rw	32.000s	53.358us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	34.000s	67.581us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	33.000s	51.252us	1	1	100.00

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				0	1	0.00
	rv_dm_smoke	30.000s	204.710us	0	1	0.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	29.000s	380.744us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	34.000s	255.389us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	269.752us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	792.864us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	40.000s	3078.849us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	29.000s	137.570us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	31.000s	195.384us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	31.000s	389.613us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	173.739us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	3549.821us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	31.000s	354.946us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	29.000s	54.214us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	33.000s	7400.342us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	51.000s	8581.213us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	29.000s	67.947us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	644.700us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	61.260us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	32.000s	242.459us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	32.000s	242.459us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	65.000s	18079.173us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	337.909us	1	1	100.00
	rv_dm_csr_rw	32.000s	53.358us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	2003.174us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	65.000s	18079.173us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	337.909us	1	1	100.00
	rv_dm_csr_rw	32.000s	53.358us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	2003.174us	1	1	100.00

V2S

6/7 passed

85.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	482.153us	1	1	100.00
	rv_dm_tl_intg_err	34.000s	1227.655us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	34.000s	1227.655us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	3549.821us	1	1	100.00
	rv_dm_debug_disabled	29.000s	115.839us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	3549.821us	1	1	100.00
	rv_dm_debug_disabled	29.000s	115.839us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				0	1	0.00
	rv_dm_smoke	30.000s	204.710us	0	1	0.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	30.000s	516.313us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	36.000s	151.850us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	36.000s	151.850us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	30.000s	516.313us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	41.000s	1235.793us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	328.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				3 test runs
	rv_dm_delayed_resp_sba_tl_access	102214119935735691225924598194310879898035777242281982570087702980853184095157	107	UVM_INFO @ 137569860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	87609217018290083535877447843593096470923853573237159163642664463157882321890	107	UVM_INFO @ 195384259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	86233472519989036244190970963442303830599367076573245525953026069253719755965	107	UVM_INFO @ 389612947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	8121328054958358963856035798416256202840603806253388043261368553853959855916	87	UVM_INFO @ 54213701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	51831167874654094860060485920544692788996688483002006341958145128350827575418	90	UVM_INFO @ 644699749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [rv_dm_smoke_vseq] expect alert:fatal_fault to fire				1 test run
	rv_dm_smoke	108060599050984166080922945602317993622908565697724654268536186935294339889715	94	UVM_INFO @ 204710318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	113413668621785856365858938362907895303384460659667354524893990500980508237296	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24243
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	18568438429379266784386265007034017355507116429886029704106713230449643466877	87	UVM_INFO @ 157762843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	95559056438208955486595004784880662819058069107890120122551962422887250224387	87	UVM_INFO @ 173738947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	58304548320312910597404906362921076620151382271950715342616614910238627848701	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	95871388372814559769097848920064453265140581071289785797544487988128942032416	112	UVM_INFO @ 1235793417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---