Simulation Results: rv_timer

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 891.234us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 15.511us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 14.543us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 102.813us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 46.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 14.543us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 201.176us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 5.000s 2757.911us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 3528.487us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 3528.487us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 12999.635us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 152.870us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 53.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 103.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 103.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.511us 1 1 100.00
rv_timer_csr_rw 2.000s 14.543us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.255us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 57.435us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.511us 1 1 100.00
rv_timer_csr_rw 2.000s 14.543us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.255us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 57.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 68.673us 1 1 100.00
rv_timer_tl_intg_err 1.000s 443.609us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 443.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 849.493us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 168.376us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 16.000s 6089.562us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 29138121535712802923664723498743387729105425875775632738876212104952884739338 84
UVM_INFO @ 849492562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 80220373087616479439689621357930779281790098401856543518312935527771695295014 85
UVM_INFO @ 201175630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 97859288128456631293251145876240557143486269210335503738426716121199890882878 84
UVM_INFO @ 168376223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---