Simulation Results: spi_device/1r1w

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.92 %
  • code
  • 91.66 %
  • assert
  • 94.64 %
  • func
  • 68.45 %
  • block
  • 98.36 %
  • line
  • 98.77 %
  • branch
  • 97.02 %
  • toggle
  • 81.25 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 133.000s 23696.977us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 94.115us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 241.906us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 11.000s 819.037us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 8.000s 321.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 59.464us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 241.906us 1 1 100.00
spi_device_csr_aliasing 8.000s 321.541us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 28.146us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 33.951us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 199.778us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 6.019us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.279us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 39.344us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 39.344us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.000s 651.517us 1 1 100.00
spi_device_tpm_sts_read 2.000s 52.624us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 11.000s 7419.035us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.000s 139.983us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 1701.867us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 1701.867us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 139.907us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 139.907us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 139.907us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 139.907us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 139.907us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.000s 187.423us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 205.000s 17681.363us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 205.000s 17681.363us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 205.000s 17681.363us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.000s 246.510us 1 1 100.00
spi_device_read_buffer_direct 4.000s 145.954us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 205.000s 17681.363us 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 61.000s 2425.398us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 2445.721us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 2445.721us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 133.000s 23696.977us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 62.000s 2322.833us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 160.000s 10109.507us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 15.408us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 37.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 5.000s 76.107us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 5.000s 76.107us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 94.115us 1 1 100.00
spi_device_csr_rw 3.000s 241.906us 1 1 100.00
spi_device_csr_aliasing 8.000s 321.541us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 25.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 94.115us 1 1 100.00
spi_device_csr_rw 3.000s 241.906us 1 1 100.00
spi_device_csr_aliasing 8.000s 321.541us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 25.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 38.747us 1 1 100.00
spi_device_tl_intg_err 19.000s 988.541us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 19.000s 988.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 180.000s 20536.161us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 83327543127214366829810662205303591623136322040447388908105016551491140006963 87
UVM_ERROR @ 5162012 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004] not found within the scope .
UVM_ERROR @ 5162012 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 15930776303181268569683844080312229104541141566070173761884868682427127518607 85
UVM_ERROR @ 981675 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x388b3d [1110001000101100111101] vs 0x0 [0])
UVM_ERROR @ 1011675 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd9a8e5 [110110011010100011100101] vs 0x0 [0])
UVM_ERROR @ 1027675 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x43f4ad [10000111111010010101101] vs 0x0 [0])
UVM_ERROR @ 1049675 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb19b0a [101100011001101100001010] vs 0x0 [0])