Simulation Results: sram_ctrl/main

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.01 %
  • code
  • 95.73 %
  • assert
  • 95.91 %
  • func
  • 93.40 %
  • block
  • 94.66 %
  • line
  • 95.25 %
  • branch
  • 91.57 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 4534.935us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 28.714us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.647us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 155.904us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 366.264us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 40.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.816us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 163.000s 16416.704us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 42.000s 3824.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 3799.998us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 132.000s 19735.061us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 117.000s 4483.531us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 52.000s 13037.425us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 29.000s 9978.567us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1746.108us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 344.100us 1 1 100.00
sram_ctrl_partial_access_b2b 246.000s 70995.279us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2707.203us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 705.173us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 6741.382us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 766.677us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 379.001us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 187.000s 25774.151us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 55.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 46.578us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 46.578us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 28.714us 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.816us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.162us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 28.714us 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.647us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.816us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3849.972us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 336.117us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 336.117us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 766.677us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 766.677us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 40.647us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1746.108us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1746.108us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1746.108us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 29.000s 9978.567us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2770.775us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3849.972us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 2655.625us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 4534.935us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 4534.935us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1746.108us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 29.000s 9978.567us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 4534.935us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1897.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 443.215us 1 1 100.00