Simulation Results: sram_ctrl/ret

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.75 %
  • code
  • 82.66 %
  • assert
  • 96.43 %
  • func
  • 93.16 %
  • block
  • 93.05 %
  • line
  • 94.06 %
  • branch
  • 88.11 %
  • toggle
  • 81.82 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 23.915us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 15.196us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.829us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 84.133us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 87.558us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 40.096us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 12.829us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 87.558us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 447.571us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 123.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 1223.750us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 249.000s 18933.650us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 5035.028us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 512.478us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1092.463us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 2451.724us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 24.652us 1 1 100.00
sram_ctrl_partial_access_b2b 129.000s 24432.518us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 122.963us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 170.926us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 43.325us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 223.723us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 29.692us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 37.000s 3483.452us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 34.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 293.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 293.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.196us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.829us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 87.558us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.451us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.196us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.829us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 87.558us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 441.876us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 693.164us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 693.164us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 223.723us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 223.723us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.829us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2451.724us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2451.724us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2451.724us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1092.463us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 32.073us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 441.876us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 71.514us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 23.915us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 23.915us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 2451.724us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1092.463us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 23.915us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1423.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 1606.863us 1 1 100.00