Simulation Results: uart

 
11/05/2026 19:40:30 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.75 %
  • code
  • 96.44 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 88.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 122.462us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 16.556us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 14.457us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 4.000s 247.994us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 57.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 37.410us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 14.457us 1 1 100.00
uart_csr_aliasing 2.000s 57.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 124.000s 81831.573us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 122.462us 1 1 100.00
uart_tx_rx 124.000s 81831.573us 1 1 100.00
parity_error 2 2 100.00
uart_intr 21.000s 49432.835us 1 1 100.00
uart_rx_parity_err 53.000s 35858.012us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 124.000s 81831.573us 1 1 100.00
uart_intr 21.000s 49432.835us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 43.000s 33091.179us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 65.000s 72569.575us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 14.000s 19677.364us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 21.000s 49432.835us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 21.000s 49432.835us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 21.000s 49432.835us 1 1 100.00
perf 1 1 100.00
uart_perf 263.000s 10154.885us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 1506.022us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 1506.022us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.000s 3782.185us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 23.000s 68486.393us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.000s 1564.609us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 4333.912us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 87.000s 82785.317us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 108.000s 476794.412us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 13.658us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 17.168us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 159.716us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 159.716us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.556us 1 1 100.00
uart_csr_rw 1.000s 14.457us 1 1 100.00
uart_csr_aliasing 2.000s 57.654us 1 1 100.00
uart_same_csr_outstanding 1.000s 30.953us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.556us 1 1 100.00
uart_csr_rw 1.000s 14.457us 1 1 100.00
uart_csr_aliasing 2.000s 57.654us 1 1 100.00
uart_same_csr_outstanding 1.000s 30.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 48.781us 1 1 100.00
uart_tl_intg_err 2.000s 191.345us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 191.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 30.000s 3121.435us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 10626489616123695378551463210117612524222501265785646881274814256447408430632 84
UVM_ERROR @ 3242954912 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3242964912 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3254384912 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 3254484912 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0