Simulation Results: ac_range_check

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.87 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 23.000s 2135.926us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 41.000s 8234.392us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 36.006us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 66.630us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 28.000s 6562.845us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1381.964us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 51.769us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 66.630us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1381.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 203.919us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 22.000s 970.244us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 44.000s 881.493us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 21.692us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 12.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 391.574us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 391.574us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.006us 1 1 100.00
ac_range_check_csr_rw 2.000s 66.630us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1381.964us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 191.648us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 36.006us 1 1 100.00
ac_range_check_csr_rw 2.000s 66.630us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1381.964us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 191.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 375.591us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 375.591us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 375.591us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 375.591us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 79.000s 35728.987us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 12.171us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 2502.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 285.000s 9159.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 23.000s 3050.167us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_stress_all 44868120663293676897261248061902991758814658649426948850427763531051234454535 9068
UVM_INFO @ 881492704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---