Simulation Results: aes/gcm_masked

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.97 %
  • code
  • 95.81 %
  • assert
  • 98.29 %
  • func
  • 66.82 %
  • block
  • 95.81 %
  • line
  • 97.49 %
  • branch
  • 89.62 %
  • toggle
  • 98.05 %
  • FSM
  • 98.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 124.989us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 244.557us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 64.052us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.983us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 199.652us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 136.309us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 126.396us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.983us 1 1 100.00
aes_csr_aliasing 3.000s 136.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 244.557us 1 1 100.00
aes_config_error 2.000s 82.509us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 244.557us 1 1 100.00
aes_config_error 2.000s 82.509us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
back2back 2 2 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_b2b 7.000s 845.638us 1 1 100.00
backpressure 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 244.557us 1 1 100.00
aes_config_error 2.000s 82.509us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 65.939us 1 1 100.00
aes_config_error 2.000s 82.509us 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 121.319us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 1067.048us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 376.697us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
stress 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
sideload 2 2 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_sideload 3.000s 514.703us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 150.837us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 44.000s 2164.989us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 194.176us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 328.352us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 244.611us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 244.611us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.052us 1 1 100.00
aes_csr_rw 2.000s 77.983us 1 1 100.00
aes_csr_aliasing 3.000s 136.309us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.060us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.052us 1 1 100.00
aes_csr_rw 2.000s 77.983us 1 1 100.00
aes_csr_aliasing 3.000s 136.309us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 143.282us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 194.536us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 3827.795us 1 1 100.00
aes_tl_intg_err 3.000s 338.952us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 338.952us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 244.557us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
aes_core_fi 5.000s 825.137us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 194.176us 1 1 100.00
aes_config_error 2.000s 82.509us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_core_fi 5.000s 825.137us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.990us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 76.445us 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 10.000s 418.201us 1 1 100.00
aes_sideload 3.000s 514.703us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 76.445us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 76.445us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 76.445us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 76.445us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 76.445us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 10.000s 418.201us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 220.600us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 220.600us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 220.600us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 220.600us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 86.251us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_ctr_fi 3.000s 58.470us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_ghash_fi 2.000s 82.003us 1 1 100.00
aes_fi 3.000s 220.600us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 220.600us 1 1 100.00
aes_control_fi 2.000s 71.700us 1 1 100.00
aes_cipher_fi 2.000s 53.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 4247.491us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
aes_stress_all_with_rand_reset 8038902118443745460781492877963930002190768931768042708790347262585068600644 329
UVM_INFO @ 4247491385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---