Simulation Results: alert_handler

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.33 %
  • code
  • 91.08 %
  • assert
  • 98.29 %
  • func
  • 78.63 %
  • line
  • 99.75 %
  • branch
  • 97.74 %
  • cond
  • 90.80 %
  • toggle
  • 88.09 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.950s 530.442us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.230s 130.163us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 163.900s 3395.326us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 57.710s 2587.603us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.740s 80.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.230s 130.163us 1 1 100.00
alert_handler_csr_aliasing 57.710s 2587.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 123.560s 4023.137us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 48.370s 4331.206us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1103.980s 34681.414us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 10.410s 126.584us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 4.510s 33.096us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 19.630s 398.869us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 351.740s 23054.478us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2433.840s 588414.786us 1 1 100.00
alert_handler_lpg_stub_clk 1229.640s 117089.340us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1403.990s 28669.403us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 27.640s 1654.847us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.060s 50.897us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.320s 6.307us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 17.310s 354.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 17.310s 354.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.950s 530.442us 1 1 100.00
alert_handler_csr_rw 5.230s 130.163us 1 1 100.00
alert_handler_csr_aliasing 57.710s 2587.603us 1 1 100.00
alert_handler_same_csr_outstanding 12.410s 243.958us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.950s 530.442us 1 1 100.00
alert_handler_csr_rw 5.230s 130.163us 1 1 100.00
alert_handler_csr_aliasing 57.710s 2587.603us 1 1 100.00
alert_handler_same_csr_outstanding 12.410s 243.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 100.240s 2012.654us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 100.240s 2012.654us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 100.240s 2012.654us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 100.240s 2012.654us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 474.780s 9415.240us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
alert_handler_tl_intg_err 34.770s 679.495us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 34.770s 679.495us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 100.240s 2012.654us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 20.560s 1740.572us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.410s 126.584us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2433.840s 588414.786us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 10.410s 126.584us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1103.980s 34681.414us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1103.980s 34681.414us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.270s 850.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 118.160s 2639.619us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 81341877657647477781298295868653273762762557383952031750351384160076822448210 206
UVM_INFO @ 1654846698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 37703012274965956794615122709438990818721866026278005206089066105417196761740 163
UVM_INFO @ 2639619243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---