Simulation Results: clkmgr

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.08 %
  • code
  • 79.50 %
  • assert
  • 93.80 %
  • func
  • 66.94 %
  • line
  • 91.49 %
  • branch
  • 93.99 %
  • cond
  • 87.19 %
  • toggle
  • 99.81 %
  • FSM
  • 25.00 %
Validation stages
V1
33.33%
V2
61.54%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.200s 65.460us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.800s 160.274us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.120s 33.601us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.770s 6.643us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.700s 5.911us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
clkmgr_csr_aliasing 0.770s 6.643us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.920s 23.068us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.000s 23.220us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.160s 71.755us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.200s 65.460us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.020s 40.723us 1 1 100.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.800s 19.184us 0 1 0.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.020s 40.723us 1 1 100.00
stress_all 0 1 0.00
clkmgr_stress_all 0.860s 26.193us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 2.180s 193.292us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.840s 72.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.840s 72.015us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.800s 160.274us 1 1 100.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
clkmgr_csr_aliasing 0.770s 6.643us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 8.104us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.800s 160.274us 1 1 100.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
clkmgr_csr_aliasing 0.770s 6.643us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 8.104us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.210s 645.251us 1 1 100.00
clkmgr_tl_intg_err 0.860s 4.473us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 47.916us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 47.916us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 47.916us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 47.916us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.770s 12.530us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.860s 4.473us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.020s 40.723us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.800s 19.184us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 47.916us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 22.275us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.210s 645.251us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 2.712us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.210s 645.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 4.161us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.170s 50.451us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 82084016980415554542932101699759497933505298519491994546446327687923722451252 78
UVM_INFO @ 19184419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 96684079347890104774134098021820314750477220610066034703992311065198091018599 85
UVM_INFO @ 50451318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 70491952650488373570439101775022991393399770356904325805675008367674363863887 78
UVM_INFO @ 26192968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 62431574017221658723687270025961725217758509231128087834363730287351373441515 75
UVM_INFO @ 12530288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14417357703335946666112721028448246080668721928101945023332812572033652142162 78
UVM_INFO @ 4473297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 18010219710817861459174561204148467213878611619619700977808045459198079005549 75
UVM_INFO @ 2711688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_csr_aliasing 99481643776479317417861979824720390744434033273178002346451047719204745994714 75
UVM_INFO @ 6643365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 46879301818971575035525104420622045118272857235285800625918293844223856712038 76
UVM_INFO @ 5911413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 16080291455571551540645009050872040219167907301387495677628111763071490856251 74
UVM_INFO @ 4161178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 108112503106086711903292819446883911276762258478260677155537537058637094201274 75
UVM_INFO @ 33600752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 35014644064010868079018875941270173205464418130872432675182731027830462962227 75
UVM_INFO @ 8103735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---