Simulation Results: dma

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.38 %
  • code
  • 92.17 %
  • assert
  • 95.87 %
  • func
  • 62.11 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 617.577us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 3961.914us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1261.667us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 34.635us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 52.183us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 1910.740us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 159.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 81.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 52.183us 1 1 100.00
dma_csr_aliasing 3.000s 159.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 66.000s 35112.612us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 306.000s 206583.866us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 265.000s 265754.528us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 265.000s 265754.528us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 306.000s 206583.866us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 190.000s 15359.795us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 265.000s 265754.528us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 2364.668us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 84.000s 16168.532us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 43.850us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 17.918us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 61.147us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 61.147us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 34.635us 1 1 100.00
dma_csr_rw 1.000s 52.183us 1 1 100.00
dma_csr_aliasing 3.000s 159.954us 1 1 100.00
dma_same_csr_outstanding 3.000s 339.259us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 34.635us 1 1 100.00
dma_csr_rw 1.000s 52.183us 1 1 100.00
dma_csr_aliasing 3.000s 159.954us 1 1 100.00
dma_same_csr_outstanding 3.000s 339.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 423.154us 1 1 100.00
dma_generic_stress 190.000s 15359.795us 1 1 100.00
dma_handshake_stress 265.000s 265754.528us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1353.797us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 183.195us 1 1 100.00
dma_sec_cm 1.000s 38.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 88.000s 5106.340us 1 1 100.00
dma_longer_transfer 3.000s 114.068us 1 1 100.00
dma_stress_all_with_rand_reset 5.000s 1372.114us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 85675738114158996569551750474112217781980760007758827812266317574096361434121 96
UVM_INFO @ 1372114100ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---