Simulation Results: edn/edn0

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.54 %
  • code
  • 79.50 %
  • assert
  • 93.58 %
  • func
  • 47.55 %
  • block
  • 92.68 %
  • line
  • 95.95 %
  • branch
  • 84.33 %
  • toggle
  • 67.93 %
  • FSM
  • 69.77 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 64.212us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 33.870us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 47.123us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 264.264us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 15.286us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 34.050us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 47.123us 1 1 100.00
edn_csr_aliasing 1.000s 15.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 49.035us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 49.035us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 49.035us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 56.095us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 51.542us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 31.522us 1 1 100.00
disable 1 2 50.00
edn_disable 1.000s 49.591us 1 1 100.00
edn_disable_auto_req_mode 5.000s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.000s 62.258us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 23.601us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 22.601us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 371.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 371.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 33.870us 1 1 100.00
edn_csr_rw 1.000s 47.123us 1 1 100.00
edn_csr_aliasing 1.000s 15.286us 1 1 100.00
edn_same_csr_outstanding 2.000s 116.633us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 33.870us 1 1 100.00
edn_csr_rw 1.000s 47.123us 1 1 100.00
edn_csr_aliasing 1.000s 15.286us 1 1 100.00
edn_same_csr_outstanding 2.000s 116.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
edn_tl_intg_err 3.000s 449.517us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 27.236us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 51.542us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 51.542us 1 1 100.00
edn_sec_cm 8.000s 644.913us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 51.542us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 449.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.000s 18791.880us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 75315400246909060194528348944955825530031671633934768891103401343055391093226 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---