Simulation Results: edn/edn1

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 82.44 %
  • assert
  • 97.14 %
  • func
  • 80.67 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 89.54 %
  • toggle
  • 87.80 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 36.818us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 104.971us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.010s 14.962us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.410s 115.360us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.050s 74.113us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 62.365us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.010s 14.962us 1 1 100.00
edn_csr_aliasing 1.050s 74.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 49.931us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 49.931us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 49.931us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 23.342us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.180s 22.622us 1 1 100.00
errs 1 1 100.00
edn_err 1.110s 27.606us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 22.356us 1 1 100.00
edn_disable_auto_req_mode 0.940s 87.067us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.340s 378.306us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 51.460us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 18.612us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.140s 79.970us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.140s 79.970us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 104.971us 1 1 100.00
edn_csr_rw 1.010s 14.962us 1 1 100.00
edn_csr_aliasing 1.050s 74.113us 1 1 100.00
edn_same_csr_outstanding 1.160s 37.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 104.971us 1 1 100.00
edn_csr_rw 1.010s 14.962us 1 1 100.00
edn_csr_aliasing 1.050s 74.113us 1 1 100.00
edn_same_csr_outstanding 1.160s 37.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
edn_tl_intg_err 1.390s 55.296us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 21.243us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.180s 22.622us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.180s 22.622us 1 1 100.00
edn_sec_cm 3.930s 356.638us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.180s 22.622us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.390s 55.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.110s 2398.818us 1 1 100.00