Simulation Results: hmac

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.06 %
  • code
  • 96.11 %
  • assert
  • 96.95 %
  • func
  • 29.13 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.000s 435.780us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 137.471us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 39.552us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.000s 4583.080us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 732.469us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 225.496us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 39.552us 1 1 100.00
hmac_csr_aliasing 5.000s 732.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.000s 4523.666us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 69.000s 4383.424us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 230.000s 97877.331us 1 1 100.00
hmac_test_sha384_vectors 23.000s 2571.870us 1 1 100.00
hmac_test_sha512_vectors 23.000s 957.454us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 245.438us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 502.556us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 270.470us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.000s 1037.241us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 232.000s 21440.614us 1 1 100.00
error 1 1 100.00
hmac_error 69.000s 26090.572us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 56.000s 25747.106us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.000s 435.780us 1 1 100.00
hmac_long_msg 26.000s 4523.666us 1 1 100.00
hmac_back_pressure 69.000s 4383.424us 1 1 100.00
hmac_datapath_stress 232.000s 21440.614us 1 1 100.00
hmac_burst_wr 7.000s 1037.241us 1 1 100.00
hmac_stress_all 96.000s 10315.079us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.000s 435.780us 1 1 100.00
hmac_long_msg 26.000s 4523.666us 1 1 100.00
hmac_back_pressure 69.000s 4383.424us 1 1 100.00
hmac_datapath_stress 232.000s 21440.614us 1 1 100.00
hmac_wipe_secret 56.000s 25747.106us 1 1 100.00
hmac_test_sha256_vectors 230.000s 97877.331us 1 1 100.00
hmac_test_sha384_vectors 23.000s 2571.870us 1 1 100.00
hmac_test_sha512_vectors 23.000s 957.454us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 245.438us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 502.556us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 270.470us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.000s 435.780us 1 1 100.00
hmac_long_msg 26.000s 4523.666us 1 1 100.00
hmac_back_pressure 69.000s 4383.424us 1 1 100.00
hmac_datapath_stress 232.000s 21440.614us 1 1 100.00
hmac_burst_wr 7.000s 1037.241us 1 1 100.00
hmac_error 69.000s 26090.572us 1 1 100.00
hmac_wipe_secret 56.000s 25747.106us 1 1 100.00
hmac_test_sha256_vectors 230.000s 97877.331us 1 1 100.00
hmac_test_sha384_vectors 23.000s 2571.870us 1 1 100.00
hmac_test_sha512_vectors 23.000s 957.454us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 245.438us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 502.556us 1 1 100.00
hmac_test_hmac512_vectors 11.000s 270.470us 1 1 100.00
hmac_stress_all 96.000s 10315.079us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 96.000s 10315.079us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 12.819us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 32.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.000s 50.082us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.000s 50.082us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 137.471us 1 1 100.00
hmac_csr_rw 2.000s 39.552us 1 1 100.00
hmac_csr_aliasing 5.000s 732.469us 1 1 100.00
hmac_same_csr_outstanding 2.000s 34.900us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 137.471us 1 1 100.00
hmac_csr_rw 2.000s 39.552us 1 1 100.00
hmac_csr_aliasing 5.000s 732.469us 1 1 100.00
hmac_same_csr_outstanding 2.000s 34.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 110.658us 1 1 100.00
hmac_tl_intg_err 4.000s 1756.982us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 1756.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.000s 435.780us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 151.923us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 28.000s 2623.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 80.154us 1 1 100.00