Simulation Results

Simulation Results: i2c

12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.08 %

code
90.00 %

assert
96.19 %

func
81.05 %

block
96.14 %

line
95.65 %

branch
93.09 %

toggle
87.10 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	86.000s	10563.669us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	18.000s	1530.031us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	43.320us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	27.044us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	218.488us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	62.874us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	79.532us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	27.044us	1	1	100.00
	i2c_csr_aliasing	3.000s	62.874us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	15.347us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	125.000s	5663.128us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	1.000s	42.608us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.097s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	741.000s	2143.369us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	551.130us	1	1	100.00
	i2c_host_fifo_fmt_empty	23.000s	1765.562us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	454.509us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	57.000s	6019.309us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	23.000s	667.235us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	15.777us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	501.973us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	71.000s	8997.524us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	10421.882us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	35.000s	4269.447us	1	1	100.00
	i2c_target_intr_smoke	6.000s	901.653us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	160.162us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	474.233us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	35.000s	4269.447us	1	1	100.00
	i2c_target_intr_stress_wr	13.000s	7295.931us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	10522.483us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	904.000s	3811.108us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	8.000s	16838.824us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	6.000s	10485.953us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	2322.468us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	51.847us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
	i2c_host_perf_precise	1.000s	79.077us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	23.000s	667.235us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	159.400us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	10382.170us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	2382.023us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	523.949us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	9.000s	1849.335us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.000s	1029.238us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	73.866us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	27.907us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	28.480us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	28.480us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	43.320us	1	1	100.00
	i2c_csr_rw	1.000s	27.044us	1	1	100.00
	i2c_csr_aliasing	3.000s	62.874us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	93.698us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	43.320us	1	1	100.00
	i2c_csr_rw	1.000s	27.044us	1	1	100.00
	i2c_csr_aliasing	3.000s	62.874us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	93.698us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	150.990us	1	1	100.00
	i2c_sec_cm	2.000s	82.303us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	150.990us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	31.000s	9090.216us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	581.056us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.000s	720.970us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				4 test runs
	i2c_host_error_intr	91773962348764675368347805803486458734850303809102220286311699153809746885945	89	UVM_INFO @ 15346877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	107643335358697708097704499250301746720239790860490729869955336908404507575624	131	UVM_INFO @ 5663128139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	115173838274341084759703239140659619965549938111563496958358279943521450641751	99	UVM_INFO @ 720969884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	62082192635470060173585368429806430640193743015311160541737296092721946670196	90	UVM_INFO @ 15776609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	115098537190295029646336705012130971832563856315242391314360619230447550115566	None
	i2c_host_perf	115223955055300566779109911009442987846807818401230779538669570708093352014714	None
	i2c_target_stress_wr	67077606554499062869150517398025597329112941218861210685434421487521748390988	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	66962772805663459070939151565358749406566465827100038409506734941106707051159	93	UVM_INFO @ 501972978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	106747868460472951121235081422565067202688663574195008059357375874499377788511	87	UVM_INFO @ 581055794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	23274795615523873328865311524740770365251743508776153372957214400793612526566	88	UVM_INFO @ 10485953109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	89443240911681713008333083302115158347142326771332324717527754559003341453216	102	UVM_INFO @ 9090215643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---