Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.58 %
  • code
  • 93.23 %
  • assert
  • 95.97 %
  • func
  • 88.54 %
  • block
  • 96.66 %
  • line
  • 97.32 %
  • branch
  • 91.49 %
  • toggle
  • 88.87 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 80.647us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 29.641us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.510us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 28.145us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 147.588us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 56.255us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 44.510us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 147.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 75.844us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1245.769us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.567us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 48.786us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 1780.492us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_prog_failure 2.000s 48.786us 1 1 100.00
lc_ctrl_errors 6.000s 1780.492us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1051.384us 1 1 100.00
lc_ctrl_jtag_state_failure 33.000s 13388.927us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 97.005us 1 1 100.00
lc_ctrl_jtag_errors 17.000s 2609.185us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 1055.304us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.000s 4248.146us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 97.005us 1 1 100.00
lc_ctrl_jtag_errors 17.000s 2609.185us 1 1 100.00
lc_ctrl_jtag_access 3.000s 87.478us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 5.000s 3058.867us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 166.272us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 48.966us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 19.000s 1353.286us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 1036.539us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 37.501us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 97.184us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 22.631us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 33.000s 8262.339us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 16.090us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.000s 8460.839us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 76.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 344.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 344.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 29.641us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.510us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 147.588us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 121.607us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 29.641us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.510us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 147.588us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 121.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 176.074us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 176.074us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1245.769us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 2013.891us 1 1 100.00
lc_ctrl_sec_cm 3.000s 854.566us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1051.384us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 75.844us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.000s 4248.146us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 2093.704us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 2093.704us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 379.700us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 216.835us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 216.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 20.000s 2606.443us 1 1 100.00