Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/05/2026 19:39:19 DVSim: v1.34.0 sha: b76d9ad json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 93.87 %
  • assert
  • 95.97 %
  • func
  • 86.62 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 87.68 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 67.912us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 29.245us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.042us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 21.583us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.043us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 42.828us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 25.042us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 215.646us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 279.493us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 18.469us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 66.598us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 703.038us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_prog_failure 2.000s 66.598us 1 1 100.00
lc_ctrl_errors 8.000s 703.038us 1 1 100.00
lc_ctrl_security_escalation 4.000s 414.639us 1 1 100.00
lc_ctrl_jtag_state_failure 29.000s 23105.477us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 470.141us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2100.204us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 160.222us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 2283.302us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 470.141us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2100.204us 1 1 100.00
lc_ctrl_jtag_access 7.000s 1763.206us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 6566.032us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 173.266us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 104.670us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 463.151us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 947.347us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 156.580us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 113.532us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 183.307us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 509.461us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 33.304us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 20.000s 9828.347us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 79.109us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 89.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 89.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 29.245us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.042us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.043us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 27.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 29.245us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.042us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.043us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 27.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 121.657us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 121.657us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 279.493us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 592.200us 1 1 100.00
lc_ctrl_sec_cm 3.000s 246.960us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 414.639us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 215.646us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 2283.302us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 614.270us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 614.270us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 559.168us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 236.201us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 236.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.000s 1125.960us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 98829042496767521110553921447832169680237571271854529989085722384289379256164 375
UVM_INFO @ 1125959665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---